Solid state charge qubit device
View Patent ↗Ionisation of one of a pair of dopant atoms in a substrate creates a double well potential, and a charge qubit is realised by the location of one or more electrons or holes within this potential. The dopant atoms may comprise phosphorous atoms, located in a silicon substrate. A solid state quantum computer may be formed using a plurality of pairs of dopant atoms, corresponding gate electrodes, and read-out devices comprising single electron transistors.
1. A quantum device, comprising:
an electrically inert solid substrate within which there is;
a charge qubit comprising a pair of dopant atoms having a net charge and an electric field having two potential wells, wherein the two potential wells are located adjacent respective dopant atoms;
and wherein a location of the net charge in the electric field having two potential wells defines a logical state of the charge qubit;
and wherein a first gate is located over a potential barrier between the two potential wells to control a barrier height; and
at least one second gate is located to control relative shapes and sizes of the two potential wells, wherein the substrate is silicon, the dopant atoms are phosphorus (P) atoms and the charge qubit is a P —P + system, whose electric field has the two potential wells.
2. A quantum device according to claim 1 , wherein the logical state of the charge qubit is defined by a location of a single electron in one of the two potential wells.
3. A quantum device according to claim 1 , wherein the logical state Of the charge qubit is defined by lowest symmetric or antisymmetric molecular states.
4. A quantum device according to claim 1 , wherein the spacing between the P atoms is up to 200 nm.
5. A quantum device according to claim 4 , wherein the spacing between the P atoms is in a range of 20 to 100 nm.
6. A quantum device according to claim 1 , wherein the two P atoms are buried in the substrate to a depth of up to 200 nm.
7. A quantum device according to claim 6 , wherein the two P atoms are buried in the substrate to a depth in a range of 5 to 50 nm.
8. A quantum device according to claim 1 , wherein the silicon substrate is coated with an insulating layer.
9. A quantum device according to claim 8 , wherein the insulating layer is Sio 2 .
10. A quantum device according to claim 1 , wherein gate Electrodes are placed on a surface of the substrate above the dopant Atoms to allow for external control of charge wavefunctions, wherein the first gate is a ‘barrier’ gate or B-gate.
11. A quantum device according to claim 10 , wherein the at least one second gate is a ‘potential off-set’, ‘symmetry’ or S-gate.
12. A quantum device according to claim 11 , wherein suitable biasing of the first and second gates allows one qubit logic operation to be performed.
13. A quantum device according to claim 10 , wherein one or more charge detection devices are provided on the surface of the substrate for charge qubit readout and to confirm initialization of charge qubits.
14. A quantum device according to claim 13 , wherein one of the one or more charge detection devices is a sensitive field-effect transistor, or a single electron transistor (SET).
15. A quantum device according to claim 1 , wherein a configuration comprising two dopant atoms, surface gates and surface charge detection devices is repeated many times on a single silicon chip, allowing for scale-up to a many charge qubit processor.
16. A quantum device according to claim 15 , wherein the device is cooled to ensure that the dopant atoms are not thermally ionised and to minimise coupling of the charge qubits to an environment.
17. A quantum device according to claim 16 , wherein the device is cooled to 4K or below.