Integrated circuit with embedded identification code
An integrated circuit ( 100 ) has a plurality of inputs ( 110 ) and a plurality of outputs ( 120 ). In a test mode, a test arrangement including a plurality of logic gates ( 140 ) is coupled between the plurality of inputs ( 110 ) and the plurality of outputs ( 120 ). The logic gates from the plurality of logic gates ( 140 ) have a first input coupled to an input of the plurality of inputs ( 110 ) and a further input coupled to a fixed logic value source ( 150 ). The fixed logic value source ( 150 ) is used to define an identification code of the integrated circuit ( 100 ), which can be retrieved at the plurality of outputs ( 120 ) when an appropriate bit pattern is fed to the plurality of inputs ( 110 ).
1. An integrated circuit, comprising:
a plurality of inputs;
a plurality of outputs;
a functional block being coupled between the plurality of inputs and the plurality of outputs only in a functional mode of the integrated circuit;
a test arrangement being coupled between the plurality of inputs and the plurality of outputs in a test mode of the integrated circuit, the test arrangement comprising a plurality of logic gates, each logic gate from the plurality of logic gates having a first input coupled to an input from the plurality of inputs; and
a programmable switch configured to switch between the functional mode and the test mode of the integrated circuit, wherein the programmable switch is coupled between an input from the plurality of inputs, the functional block and the first input of each logic gate from the plurality of logic gates,
characterized by each logic gate from the plurality of gates having a further input coupled to a fixed logic value source.
2. An integrated circuit as claimed in claim 1 , characterized in that the plurality of logic gates comprises exclusive logic gates.
3. An integrated circuit as claimed in claim 1 , characterized in that the fixed logic value source is programmable.
4. An integrated circuit as claimed in claim 1 , characterized by further comprising a plurality of multiplexers, a multiplexer from the plurality of multiplexers being responsive to a select signal, the multiplexer having a first input coupled to an input from the plurality of inputs, a second input coupled to the fixed logic value source of a logic gate from the plurality of logic gates and an output coupled to the further input of the logic gate.
5. An integrated circuit as claimed in claim 4 , characterized in that the select signal is provided by the test arrangement.
6. An integrated circuit as claimed in claim 4 , characterized in that the select signal is provided via a dedicated input from the plurality of inputs.
7. An integrated circuit, comprising:
a plurality of inputs;
a plurality of outputs;
a test arrangement being coupled between the plurality of inputs and the plurality of outputs in a test mode of the integrated circuit, the test arrangement comprising a plurality of logic gates, each logic gate from the plurality of logic gates having a first function and a second function, each logic gate from the plurality of logic gates having a first input coupled to an input from the plurality of inputs; and
a plurality of multiplexers, a multiplexer from the plurality of multiplexers being responsive to a select signal, the multiplexer having a first input coupled to an input from the plurality of inputs, a second input coupled to the fixed logic value source of a logic gate from the plurality of logic gates and an output coupled to the further input of the logic gate, wherein the logic gate performs the first function when the multiplexer is switched to the input from the plurality of inputs and the second function when the multiplexer is switched to the fixed logic value source of the logic gate,
characterized by each logic gate from the plurality of gates having a further input coupled to a fixed logic value source.
8. An integrated circuit as claimed in claim 7 , characterized by further comprising a functional block being coupled between the plurality of inputs and the plurality of outputs in a functional mode of the integrated circuit.
9. An integrated circuit as claimed in claim 7 , characterized in that the plurality of logic gates comprises exclusive logic gates.
10. An integrated circuit as claimed in claim 7 , characterized in that the fixed logic value source is programmable.
11. An integrated circuit as claimed in claim 7 , characterized in that the select signal is provided by the test arrangement.
12. An integrated circuit as claimed in claim 7 , characterized in that the select signal is provided via a dedicated input from the plurality of inputs.
13. An integrated circuit, comprising:
a plurality of inputs;
a plurality of outputs; and
a test arrangement being coupled between the plurality of inputs and the plurality of outputs in a test mode of the integrated circuit, the test arrangement comprising a plurality of logic gates, each logic gate from the plurality of logic gates having a first input coupled to an input from the plurality of inputs;
characterized by each logic gate from the plurality of gates having a further input coupled to a fixed logic value source, wherein the fixed logic value source includes a plurality of subsources, each subsource being arranged to provide the further input of at least one logic gate from the plurality of logic gates with a fixed logic value.
14. An integrated circuit as claimed in claim 13 , characterized by further comprising a functional block being coupled between the plurality of inputs and the plurality of outputs in a functional mode of the integrated circuit.
15. An integrated circuit as claimed in claim 13 , characterized in that the plurality of logic gates comprises exclusive logic gates.
16. An integrated circuit as claimed in claim 13 , characterized in that the fixed logic value source is programmable.
17. An integrated circuit as claimed in claim 13 , characterized by further comprising a plurality of multiplexers, a multiplexer from the plurality of multiplexers being responsive to a select signal, the multiplexer having a first input coupled to an input from the plurality of inputs, a second input coupled to the fixed logic value source of a logic gate from the plurality of logic gates and an output coupled to the further input of the logic gate.
18. An integrated circuit as claimed in claim 17 , characterized in that the select signal is provided by the test arrangement.
19. An integrated circuit as claimed in claim 18 , characterized in that the select signal is provided via a dedicated input from the plurality of inputs.