Method of fabricating a field effect transistor
View Patent ↗A field effect transistor in which at least one vertically arranged semiconductor column, with a diameter in the nanometer range, is located between a source and a contact and has an annular surround of a gate contact with retention of an insulation gap. A simplified production method is disclosed and the transistor produced thus is embodied such that the semiconductor columns are embedded in a first and a second insulation layer, between which a metal layer, running to the outside as a gate contact, is arranged, the ends of which, extending upwards through the second insulation layer, are partly converted into an insulator, or removed and replaced by an insulation material.
1. A method of fabricating a field effect transistor in which at least one vertically aligned semiconductor column of a diameter in the nanometer range is present between a source electrode and a drain electrode and is annularly surrounded by a gate electrode with an insulating space between them,
the method comprising:
free-standing semiconductor columns are grown vertically on a conductive substrate;
a first insulating layer is deposited on the semiconductor columns;
a first conductive metal layer and a second insulating layer are deposited thereon;
the developing laminate is etched planar to the point of the portion of the first conductive metal layer covering the semiconductor columns is removed again;
the end of the first conductive metal layer penetrating to the surface of the laminate are etched back in a metal-specific manner and a third insulating layer is deposited on the laminate with subsequent renewed planar etching;
or
the ends of the first conductive metal layer penetrating to the surface of the laminate are converted to an insulator by oxidizing or nitriding; and
finally depositing a second conductive metal layer on the laminate.
2. The method of claim 1 ,
wherein the laminate or individual layers are divided into individual arrays by a lithographic process.
3. The method of claim 1 ,
wherein the growing of the semiconductor columns is carried out electro-chemically.
4. The method of claim 1 ,
wherein the growing of the semiconductor columns is carried out by sputtering.
5. The method of claim 1 ,
wherein the growing of the semiconductor columns is carried out by a CVD process.
6. The method of claim 1 ,
wherein the growing of the semiconductor columns is carried out by vaporization.
7. The method of claim 1 ,
wherein the growing of the semiconductor columns is carried out in ion trace channels of a polymeric film which is subsequently removed.