IP Library Granted Patent US 7,565,389
Granted Patent B2
US 7,565,389 · App. 10/532,903 · Granted Jul 21, 2009

Method for determining filter coefficients of a digital filter and digital filter

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Quick Facts
Patent No.
US 7,565,389
App. No.
10/532,903
Granted
Jul 21, 2009
Kind
B2
Abstract

In a method for determining filter coefficients of a digital filter, particularly in UMTS, the predetermined filter coefficients bv are divided by a same scaling factor s and then quantized in that counted from the most significant bit onwards only a certain number n of “1” bits is used and in that the quantization error E(s) is minimized by the selection of the scaling factor s0 and these scaled and quantized filter coefficients βv are implemented in the filter.

Claims (41)

1. A method, comprising:

determining a plurality of filter coefficients for a digital filter for a Universal Mobile Telecommunication System (UMTS), the determining including:

dividing initial filter coefficient by a scaling factor, to result in a plurality of scaled filter coefficients:

quantizing the scaled filter coefficient so that only a certain maximum number (n) of “1” bits are counted from a most significant bit onwards:

determining a respective quantization error of each quantized scaled filter coefficient relative to a respective one of the initial filter coefficients; and

repeatedly modifying for a number of times the scaling factor and determining which scaling factor results in a quantization error having minimal error value, and

implementing in the filter the filter coefficients resulting in the minimal error value.

2. A method as claimed in claim 1 , wherein the number (n) comprises one of four, three, or two.

3. A method as claimed in claim 1 , wherein if again a “1” bit follows the last “1” bit, a rounding is effected from the last bit onwards.

4. The new method according to claim 1 , further comprising multiplying an input by 2 j by shifting the input by i and summing shifted values using a plurality of adders.

5. The method according to claim 4 , wherein the multiplying is performed using a plurality of multipliers, the method further comprising selectively connecting the multipliers with the adders using a programmable selector in accordance with a programming.

6. The method according to claim 1 , further comprising:

multiplying an input by 2 j by shifting the input by i using a multiplier formed by connections of inputs and outputs.

7. A digital filter for a Universal Mobile Telecommunication System (UMTS), comprising

means for dividing a plurality of binary filter coefficients by a scaling factor to result in a plurality of scaled filter coefficients;

means for quantizing the scaled filter coefficients so that they do not exceed a selected number (n) of “1” bits from a most significant bit onwards; and

adder stages for processing the scaled and quantized filter coefficients with an input signal.

8. The digital filter as claimed in claim 7 , comprising a final stage for processing an output signal by a factor reciprocal to the scaling factor.

9. A digital filter as claimed in claim 7 , wherein each adder stage comprises n−1 adders and means for multiplying an input by 2 i by shifting the input by i, the input being a respective one of the scaled and quantized filter coefficients.

10. A digital filter as claimed in claim 7 , wherein the adder stages include first and second adder stages respectively including:

respective numbers of multiplying means for multiplying an input by 2 i by shifting the input by i, wherein the respective numbers of multiplying means are different: and

respective numbers of adders coupled to the respective multiplying means, wherein the respective numbers of adders are different.

11. A digital filter as claimed 10 , wherein the adder stages include a third adder stage having only a single multiplying means for multiplying an input by 2 j by shifting the input by i.

12. A digital filter as claimed in claim 7 , wherein each adder stage comprises n-1 adders and means for multiplying an input by 2 j by shifting the input by i, the input being a respective one of the scaled and quantized filter coefficients, wherein each of the means for multiplying the input by 2 i by shifting the input by i is formed by connections of inputs and outputs of a multiplier stage.

13. A digital filter as claimed in claim 7 , wherein each adder stage comprises:

n-1 adders;

multiplying means for multiplying an input by 2 j by shifting the input by j, the input being a respective one of the scaled and quantized filter coefficients; and

a programmable selector which in accordance with programming connects the multiplying means with the adders.

14. A method, comprising:

producing a plurality of scaled filter coefficients by dividing initial filter coefficients by a scaling factor;

quantizing the scaled filter coefficients so that only a certain maximum number (n) of “1” bits are counted from a most significant bit onwards;

determining respective quantization errors of the quantized scaled filter coefficients relative to the initial filter coefficients, respectively; and

modifying the scaling factor and determining which scaling factor results in a quantization error having minimal error value, and

implementing in the filter the filter coefficients resulting in the minimal error value.

15. A method as claimed in claim 14 , wherein the number (n) comprises one of four, three, or two.

16. A method as claimed in claim 14 , wherein if again a “1” bit follows the last “1” bit, a rounding is effected from the last bit onwards.

17. The method according to claim 14 , further comprising:

multiplying an input by 2 j by shifting the input by i using a multiplier formed by connections of inputs and outputs.

18. The method according to claim 14 , further comprising

multiplying an input by 2 j by shifting the input by i and summing shifted values using a plurality of adders.

19. The method according to claim 18 , wherein the multiplying is performed using a plurality of multipliers, the method further comprising selectively connecting the multipliers with the adders using a programmable selector in accordance with a programming.

Assignments (5)
CHANGE OF NAME Recorded Feb 2, 2016
From: ST WIRELESS SA
To: ST-ERICSSON SA
Reel/Frame 037683/0128 →
STATUS CHANGE-ENTITY IN LIQUIDATION Recorded Feb 2, 2016
From: ST-ERICSSON SA
To: ST-ERICSSON SA, EN LIQUIDATION
Reel/Frame 037739/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2016
From: NXP B.V.
To: ST WIRELESS SA
Reel/Frame 037624/0831 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2005
From: RUNZE, GERHARD
To: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
Reel/Frame 017020/0019 →