IP Library Granted Patent US 7,304,383
Granted Patent B2
US 7,304,383 · App. 10/535,304 · Granted Dec 4, 2007

TFT substrate for liquid crystal display apparatus and method of manufacturing the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,304,383
App. No.
10/535,304
Granted
Dec 4, 2007
Kind
B2
Abstract

There are provided a TFT substrate for an LCD apparatus and a method of manufacturing the same. A substrate ( 10 ), a diffusion barrier layer ( 11 ) and a copper alloy layer ( 12 ) are formed on the TFT substrate, consecutively. The copper alloy includes a material from about 0.5 at % to about 15 at % to form a gate wiring layer. The material is used to form the diffusion barrier layer ( 11 ). A compound that comprises a material such as Zr, Ti, Hf, V, Ta, Ni, Cr, Nb, Co, Mn, Mo, W, Rh, Pd, Pt, etc. is deposited on the diffusion barrier layer ( 11 ) to a thickness from about 50 Å to about 5,000 Å. The deposited compound is then heat treated to convert the deposited compound into a silicide compound ( 11 b ). The transistor substrate has low resistance and high conductance. Also, etching process is simplified, and a mutual diffusion is prevented by means of the thin diffusion barrier layer.

Claims (8)

1. A TFT substrate for an LCD apparatus comprising:

a silicon-containing substrate;

a diffusion barrier layer formed directly on the substrate; and

a copper alloy layer formed on the diffusion barrier layer, the copper alloy layer including a material from about 0.5 at % to about 15 at %, which is used to form the diffusion barrier layer.

2. The TFT substrate of claim 1 , wherein the diffusion barrier layer comprises a silicide compound including at least one selected from the group consisting of Zr, Ti, Hf, V, Ta, Ni, Cr. Nb, Co, Mn, Mo, W, Rh, Pd and Pt.

3. The TFT substrate of claim 1 , wherein a thickness of the diffusion barrier layer is from about 50 Å to about 5,000 Å.

4. The TFT substrate of claim 1 , wherein the copper alloy layer is a metal layer corresponding to a gate line, a source-drain electrode or a data line.

5. The TFT substrate of claim 1 , wherein the silicon-containing substrate is a silicon substrate, a glass substrate or a plastic substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 028984/0774 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2006
From: CHO, BEOM-SEOK; JEONG, CHANG-OH
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 017184/0787 →