Processing system including a reconfigurable channel infrastructure comprising a control chain with combination elements for each processing element and a programmable switch between each pair of neighboring processing elements for efficient clustering of processing elements

1. A processing system comprising a plurality of processing elements, the processing elements comprising a controller and computation means, the plurality of processing elements being dynamically reconfigurable by a cluster control signal as mutually independently operating task units that comprise one processing element or a cluster of two or more processing elements, the processing elements within a cluster being arranged to execute instructions under a common thread of program control, wherein the cluster control signal is derived from intermediate control signals transmitted through a reconfigurable channel infrastructure connected to the processing elements, wherein the reconfigurable channel infrastructure comprises a control chain with combination elements for each processing element and a programmable switch between each pair of neighboring processing elements for locally controllably inhibiting transmission of intermediate control signals to a preceding or a succeeding processing element.

2. Processing system according to claim 1 , wherein processing elements organized in a task unit share the cluster control signal for controlling instruction execution.

3. Processing system according to claim 2 , wherein the cluster control signal is a flag controlling a guarded operation.

4. Processing system according to claim 3 , wherein the guarded operation is a conditional jump.

5. Processing system according to claim 1 , wherein the processing elements are connected to each other via data-path connections.

6. Processing system according to claim 5 , wherein the data-path connections are limited to neighbor-to-neighbor connections.

7. Processing system according to claim 1 , wherein the cluster control signal is derived by combining the intermediate control signals through a combination element associated with each processing element.

8. Processing system according to claim 7 , wherein the combination element associated with each processing element consists of an OR-gate.

9. Processing system according to claim 1 , wherein the reconfigurable channel infrastructure comprises programmable sum-terms.

10. Processing system according to claim 1 , wherein the reconfigurable channel infrastructure comprises programmable product-terms.

11. Processing system according to claim 1 , wherein the reconfigurable channel infrastructure comprises mutually transverse chains.

12. Processing system according to claim 11 , wherein the combination elements are arranged in chains having a first orientation and chains having a second orientation, and wherein the intermediate control signals transmitted through the chains having the first orientation are forwarded to the combination elements in the chains having the second orientation.

13. Processing system according to claims 12 , wherein the intermediate control signals transmitted through the chains having the second orientation are forwarded to the combination elements in the chains having the first orientation.

14. Processing system according to claim 1 , wherein the combination elements consist of OR-gates.

15. Processing system according to claim 1 , wherein the programmable switch between neighboring processing elements comprises AND-gates.

16. Processing system according to claims 1 , wherein the programmable switch between neighboring processing elements is programmed by a signal stored in a memory cell.

17. Processing system according to claim 16 , wherein at least one of the processing elements can write to at least one memory cell.

18. Processing system according to claim 16 , wherein a set of memory cells used to program a set of the programmable switches between neighboring processing elements is organized as a data-word in a memory.

19. Processing system according to claim 18 , wherein the memory contains multiple data-words, and wherein the programmable switches are programmed by selecting one of the data-words.

20. Processing system according to claims 19 , wherein one or more of the processing elements can program the programmable switches by dynamically selecting the data-word in memory.

21. Processing system according to claims 16 , wherein the memory consists of volatile random access memory.

22. Processing system according to claim 1 , wherein each single processing element is capable of executing a VLIW instruction.

23. Processing system according to claim 22 , wherein the processing element comprises an internal interconnect network.

24. Processing system according to claim 23 , wherein the internal interconnect network consists of point-to-point connections.

25. Processing system according to claim 23 , wherein the internal interconnect network comprises data-path connections to a set of operation issue slots within the processing elements.

26. Processing system according to claim 1 , wherein the processing elements are arranged in a 2-dimensional grid.

27. Method for operating a processing system comprising a plurality of processing elements, the processing elements comprising a controller and computation means, the method comprising the steps of:

combining, by a combination element, an intermediate control signal with an operation control signal of a processing element and selectively passing the combined signal to a further processing element,

deriving a cluster control signal from an operation control signal and two or more intermediate control signals, and

dynamically reconfiguring a processing element by the cluster control signal thereby dynamically reconfiguring the plurality of processing elements as mutually independently operating task units that comprise one processing element or a cluster of two or more processing elements, wherein the processing elements within a cluster execute instructions under a common thread of program control.