Method for using a synchronous sampling design in a fixed-rate sampling mode
View Patent ↗The present application generally relates to apparatuses such as television signal processing apparatus that process radio frequency signals. More specifically, the present application is particularly useful in integrated circuits that must combine circuitry operating in a synchronous-sampling mode that must be adapted for use with a fixed rate sampling mode application. According to an exemplary embodiment, the television signal processing apparatus comprises a source of a fixed rate digital signal, signal processing circuitry operating in a synchronous-sampling mode wherein the signal processing circuitry comprises a signal representing a symbol rate, and an interpolator for processing the fixed rate digital signal to yield samples at the symbol rate.
1. A signal processing apparatus comprising:
a source of a fixed rate digital signal;
a signal processor responsive to a burst clock generated by a clock generator, said signal processor operating in a synchronous-sampling mode for producing a control signal representing a symbol rate; and
an interpolator operated using a fixed rate clock and responsive to said control signal for processing the fixed rate digital signal to yield samples at the symbol rate by calculating a symbol value at a symbol location by interpolating a number of fixed rate samples adjacent to said symbol location and outputting the samples to the signal processor, and said interpolator being further operative to enable said burst clock in response to said samples at the symbol rate being ready to be processed by said signal processor.
2. The signal processing apparatus of claim 1 wherein the interpolator processes the fixed rate digital signal to yield samples at the symbol rate by calculating a symbol value at a symbol location by interpolating a number of fixed rate samples adjacent to the symbol location.
3. The signal processing apparatus of claim 1 wherein the source of the fixed rate digital signal is an analog to digital converter.
4. The signal processing apparatus of claim 1 wherein the interpolator is a cubic interpolator.
5. The signal processing apparatus of claim 1 wherein the interpolator is a linear interpolator.
6. The signal processing apparatus of claim 1 wherein the interpolator is a piecewise parabolic interpolator.
7. The signal processing apparatus of claim 1 wherein the interpolator is internal to an integrated circuit.
8. The signal processing apparatus of claim 1 wherein the interpolator is implemented using software.
9. A method of signal processing comprising the steps of:
receiving a plurality of digital values at a fixed rate of time;
receiving a control signal representing a symbol rate from a signal processor operating in a synchronous-sampling mode, said signal processor being responsive to a burst clock generated by a clock generator;
calculating a signal level at a symbol location using an interpolator responsive to said control signal by interpolating the signal level from the plurality of digital values of a number of fixed rate samples adjacent to said symbol location to yield samples at the symbol rate, wherein said interpolator operated using a fixed rate clock; and
enabling said burst clock in response to said samples at the symbol rate and said calculated signal level being available to said signal processor.
10. The method of claim 9 wherein the control signal from the signal processor is a symbol rate.
11. The method of claim 9 wherein the source of the plurality of digital values at a fixed rate of time is an analog to digital converter.
12. The method of claim 9 wherein the step of calculating a signal level by interpolating the signal level from the plurality of digital values is preformed using a cubic interpolator.
13. The method of claim 9 wherein the step of calculating a signal level by interpolating the signal level from the plurality of digital values is preformed using a linear interpolator.
14. The method of claim 9 wherein the step of calculating a signal level by interpolating the signal level from the plurality of digital values is preformed using a piecewise parabolic interpolator.
15. A signal processing apparatus comprising:
a source of an analog signal;
an analog to digital converter for converting the analog signal to a fixed rate digital signal;
a demodulator operating in a synchronous-sampling mode;
a processor responsive to a burst clock generated by a clock generator, said processor operative for producing a control signal representing a symbol rate; and
an interpolator operated using a fixed rate clock and responsive to said control signal for processing the fixed rate digital signal to yield samples at the symbol rate by calculating a symbol value at a symbol location by interpolating a number of fixed rate samples adjacent to said symbol location and outputting the samples to the demodulator, and said interpolator being further operative to enable said burst clock in response to said samples at the symbol rate being ready to be processed by said signal processor.
16. The signal processing apparatus of claim 15 wherein the interpolator is a cubic interpolator.
17. The signal processing apparatus of claim 15 wherein the interpolator is a linear interpolator.
18. The signal processing apparatus of claim 15 wherein the interpolator is a piecewise parabolic interpolator.
19. The signal processing apparatus of claim 15 wherein the interpolator is internal to an integrated circuit.
20. The signal processing apparatus of claim 15 wherein the interpolator is implemented using software.