IP Library Granted Patent US 7,338,827
Granted Patent B2
US 7,338,827 · App. 10/547,968 · Granted Mar 4, 2008

Nitride semiconductor laser and method for fabricating the same

Assignee: Matsushita Electric Industrial Co., Ltd.
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Quick Facts
Patent No.
US 7,338,827
App. No.
10/547,968
Granted
Mar 4, 2008
Kind
B2
Abstract

A method for fabricating nitride semiconductor devices according to the present invention includes the steps of: (A) providing a nitride semiconductor substrate, which will be split into chip substrates, which includes device portions that will function as the respective chip substrates when the substrate is split and interdevice portions that connect the device portions together, and in which the average thickness of the interdevice portions is smaller than the thickness of the device portions; (B) defining a masking layer, which has striped openings over the device portions, on the upper surface of the nitride semiconductor substrate; (C) selectively growing nitride semiconductor layers on portions of the upper surface of the nitride semiconductor substrate, which are exposed through the openings of the masking layer; and (D) cleaving the nitride semiconductor substrate along the interdevice portions of the nitride semiconductor substrate, thereby forming nitride semiconductor devices on the respectively split chip substrates.

Claims (15)

1. A method for fabricating nitride semiconductor lasers, the method comprising the steps of:

(A) providing a nitride semiconductor substrate, which will be split into a plurality of chip substrates, which includes a plurality of device portions that will function as the respective chip substrates when the substrate is split and a plurality of interdevice portions that connect the device portions together, and in which the average thickness of some of the interdevice portions, which extend parallel to a resonant cavity length direction, is smaller than the thickness of the other portions of the nitride semiconductor substrate;

(B) defining a masking layer, which has striped openings over the device portions, on the upper surface of the nitride semiconductor substrate;

(C) selectively growing nitride semiconductor layers on portions of the upper surface of the nitride semiconductor substrate, which are exposed through the openings of the masking layer; and

(D) subjecting the nitride semiconductor substrate to a first cleavage process perpendicularly to the resonant cavity length direction and then subjecting the nitride semiconductor substrate to a second cleavage process along the interdevice portions that extend parallel to the resonant cavity length direction, thereby forming a plurality of nitride semiconductor devices on the respectively split chip substrates,

wherein the step (A) includes the steps of:

(a1) providing a nitride semiconductor substrate with a flat upper surface; and

(a2) cutting grooves on the upper surface of the substrate, thereby making the average thickness of the interdevice portions smaller than the thickness of the device portions;

and the step (B) includes the step of:

defining the masking layer so as to cover the grooves cut in step (a2).

2. The method of claim 1 , wherein the step (a1) includes providing a GaN based compound semiconductor substrate of which the upper surface is a (0001) plane, and

wherein the step (a2) includes cutting grooves extending in the <1-100> direction.

3. The method of claim 2 , wherein the step (a2) includes the step of cutting the grooves by etching the upper surface of the substrate to a depth of at least 0.1 μm.

4. The method of claim 1 , wherein the step (C) includes forming a multilayer structure, including GaN based compound semiconductor layers, by a selective growth process.

5. The method of claim 1 , wherein when the cleaving step (D) is carried out, the overall thickness of nitride semiconductor layers deposited on the interdevice portions of the nitride semiconductor substrate is smaller than that of the nitride semiconductor layers deposited on the device portions.

Assignments (2)
CHANGE OF NAME Recorded Nov 20, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021930/0876 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2006
From: SUGAHARA, GAKU; KAWAGUCHI, YASUTOSHI; ISHIBASHI, AKIHIKO; KIDOGUCHI, ISAO; YOKOGAWA, TOSHIYA
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 018085/0808 →
Priority Claims (1)
JP 2003-082400 · Mar 25, 2003 · national
Continuity (1)
Related Publication 20060166478A1 · Jul 27, 2006