IP Library Granted Patent US 7,352,235
Granted Patent B2
US 7,352,235 · App. 10/548,252 · Granted Apr 1, 2008

Current mirror

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Quick Facts
Patent No.
US 7,352,235
App. No.
10/548,252
Granted
Apr 1, 2008
Kind
B2
Abstract

The present invention relates to Current mirror for generating a constant mirror ratio, comprising an output transistor (T ou t) having a base, an emitter and a collector, wherein a current flowing through the collector of said output transistor (T out ) constitutes an output current (I out ) of said current mirror and the collector of said output transistor (T out ) is connectable to an output circuit, a buffer transistor having a base, an emitter and a collector, wherein the emitter of the buffer transistor is connected to the base of the output transistor, a buffer current source for providing a fixed buffer current, wherein said buffer current source is connected to the collector of the buffer transistor, and a buffer base voltage control means having an input connected to the base of the output transistor and an output connected to the base of the buffer transistor, wherein the base voltage control means is adapted to controlling a voltage at the base of the buffer transistor in response to a current at the input of the buffer base voltage control means.

Claims (11)

1. Current mirror for generating a constant mirror ratio between an output current and an input current, comprising:

an output transistor having a base, an emitter and a collector, wherein a current flowing through the collector of said output transistor constitutes said output current of said current mirror and the collector of said output transistor is connectable to an output circuit,

a buffer transistor having a base, an emitter and a collector, wherein the emitter of the buffer transistor is connected to the base of the output transistor,

an input conductor, wherein the input conductor is connected to the base of the buffer transistor and an input resistor and the input conductor is connectable to an input current source providing said input current,

a buffer current source for providing a fixed buffer current, wherein said buffer current source is connected to the collector of the buffer transistor, and

a buffer base voltage control means having an input connected to the base of the output transistor and an output connected to the base of the buffer transistor, wherein the base voltage control means is adapted to controlling a voltage at the base of the buffer transistor in response to a current at the input of the buffer base voltage control means.

2. Current mirror according to claim 1 , wherein the buffer base voltage control means comprises a buffer current mirror having an input and an output, wherein the input of the buffer current mirror constitutes the input of the buffer base voltage control means and the output of the buffer current mirror constitutes the output of the buffer base voltage control means.

3. Current mirror according to claim 2 , wherein the buffer current mirror comprises a buffer current mirror input transistor having a base, a collector and an emitter, wherein the collector of the buffer current mirror input transistor constitutes the input of the current mirror, and a buffer current mirror output transistor having a base, a collector and an emitter, wherein the collector of the buffer current mirror output transistor constitutes the output of the buffer current mirror and the base of the buffer current mirror output transistor and the base of the buffer current mirror input transistor are connected to each other.

4. Current mirror according to claim 2 , wherein a buffer mirror ratio of the buffer current mirror is chosen to be the reciprocal value of the mirror ratio of the current mirror.

5. Current mirror according to claim 3 , wherein the buffer current mirror further comprises a PMOS transistor having a gate, a source and a drain, wherein the source of the PMOS transistor is connected to the collector of the buffer transistor and the drain of the PMOS transistor is connected to the base of the buffer current mirror input transistor.

6. Current mirror according to claim 3 , wherein the buffer current mirror further comprises a pnp-type bipolar transistor having a base, a collector and an emitter, wherein the emitter of the pnp-type bipolar transistor is connected to the collector of the buffer transistor and the collector of the pnp-type bipolar transistor is connected to the base of the buffer current mirror input transistor.

Assignments (5)
CHANGE OF NAME Recorded Feb 2, 2016
From: ST WIRELESS SA
To: ST-ERICSSON SA
Reel/Frame 037683/0128 →
STATUS CHANGE-ENTITY IN LIQUIDATION Recorded Feb 2, 2016
From: ST-ERICSSON SA
To: ST-ERICSSON SA, EN LIQUIDATION
Reel/Frame 037739/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2016
From: NXP B.V.
To: ST WIRELESS SA
Reel/Frame 037624/0831 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2005
From: VEENSTRA, HUGO; HURKX, GODEFRIDUS ADRIANUS MARIA; BREKELMANS, JOHANNES HUBERTUS ANTONIUS; VAN GOOR, DAVE WILLEM
To: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
Reel/Frame 017750/0019 →