IP Library Granted Patent US 7,595,476
Granted Patent B2
US 7,595,476 · App. 10/548,753 · Granted Sep 29, 2009

Electrical circuit, apparatus and method for the demodulation of an intensity-modulated signal

Assignee: CSEM Centre Suisse D'Electronique Et De Microtechnique SA
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,595,476
App. No.
10/548,753
Granted
Sep 29, 2009
Kind
B2
Abstract

A modulated optical radiation field (I) whose modulation amplitude and temporal phase depend on the local position can be detected with a plurality of pixels 1 . Each pixel 1 consists of a transducing stage (T) that converts incoming light (I) into a proportional electric signal, a sampling stage (S), two subtraction/summation stages (SUB 1 , SUM 1 ; SUB 2 , SUM 2 ), and an output stage. Each pixel can be addressed individually. The optical radiation field (I) is locally sensed and sampled at a frequency that is four times the wavefield's modulation frequency. The subtraction/summation stages (SUB 1 , SUM 1 ; SUB 2 , SUM 2 ) accumulate differences of two samples per modulation period, separated by half the period, during several averaging periods; the two stages are time shifted with respect to each other by a quarter period. The resulting two output signals are employed for the determination of the local envelope amplitude and the temporal phase. These pixels 1 can be realized with circuits that consume very little electric power require small areas, enabling the realization of large numbers of pixels in linear or two-dimensional array sensors.

Claims (51)

1. An electrical circuit for the detection of a signal (I) modulated with a modulation frequency, a modulation period being defined as the inverse of the modulation frequency, comprising:

transduction means (T) for transducing the modulated signal (I) into an electrical signal,

sampling means (S) for sampling said electrical signal with a sampling frequency which is equal to four times the modulation frequency or a multiple thereof,

first subtraction means (SUB 1 ) for evaluating a plurality of first difference between two samples per modulation period, each separated by half the modulation period, and

second subtraction means (SUB 2 ) for evaluating a plurality of second difference between two samples per modulation period, each separated by half the modulation period, said second samples being time-shifted with respect to said first samples by a defined fraction, preferably a quarter, of the modulation period,

characterized by

first summation means (SUM 1 ) for evaluating a first sum of a plurality of subsequent first differences evaluated by said first subtraction means (SUB 1 ), and

second summation means (SUM 2 ) for evaluating a second sum of a plurality of subsequent second differences evaluated by said second subtraction means (SUB 2 ).

2. The electrical circuit according to claim 1 , wherein said transduction means (T) comprise a photodiode (PD) and preferably a source follower (MP 2 , MP 3 ) for amplifying an electrical output signal of said photodiode (PD).

3. The electrical circuit according to claim 2 , wherein a storage node (SN) is arranged between said photodiode (PD) and said source follower (MP 2 , MP 3 ).

4. The electrical circuit according to claim 3 , wherein a current source (MP 5 ) for introducing a current equivalent to a photogenerated DC current through said photodiode (PD) is connected in series with said photodiode (PD).

5. The electrical circuit according to claim 4 , wherein said sampling means (S) comprise at least two switches and/or a storage node.

6. The electrical circuit according to claim 5 , further comprising:

pre-processing means (PP) for pre-processing said first and second sum evaluated by said first and second summation means (SUM 1 , SUM 2 ), respectively, e.g., for calculating a sum of the squares of said first and second sums or for calculating a ratio of said first and second sums; and

readout means (RO) for reading out an output signal of said electrical circuit.

7. A one-dimensional or two-dimensional array sensor comprising a plurality of pixels ( 1 . 11 - 1 . nm ),

characterized in that

at least one, and preferably each, of said pixels ( 1 . 11 - 1 .nm ) comprises an electrical circuit according to claim 6 .

8. An apparatus for the demodulation of a modulated signal (I), comprising:

detection means for detecting the modulated signal (I), and evaluation means (EV) for evaluating an envelope amplitude and/or a temporal phase from an output of said detection means,

characterized in that

said detection means comprise an electrical circuit ( 1 . 11 - 1 . nm ) according to claim 6 .

9. The electrical circuit according to claim 2 , wherein a current source (MP 5 ) for introducing a current equivalent to a photogenerated DC current through said photodiode (PD) is connected in series with said photodiode (PD).

10. A one-dimensional or two-dimensional array sensor comprising a plurality of pixels ( 1 . 11 - 1 . nm ),

characterized in that

at least one, and preferably each, of said pixels ( 1 . 11 - 1 .nm ) comprises an electrical circuit according to claim 9 .

11. An apparatus for the demodulation of a modulated signal (I), comprising:

detection means for detecting the modulated signal (I), and evaluation means (EV) for evaluating an envelope amplitude and/or a temporal phase from an output of said detection means,

characterized in that

said detection means comprise an electrical circuit ( 1 . 11 - 1 . nm ) according to claim 9 .

12. The electrical circuit according to claim 1 , wherein said sampling means (S) comprise at least two switches and/or a storage node.

13. The electrical circuit according to claim 1 , wherein said transduction means (T) and said sampling means (S) are combined into one element, e.g., a drift field modulation pixel or a lock-in pixel.

14. The electrical circuit according to claim 1 , further comprising pre-processing means (PP) for pre-processing said first and second sum evaluated by said first and second summation means (SUM 1 , SUM 2 ), respectively, e.g., for calculating a sum of the squares of said first and second sums or for calculating a ratio of said first and second sums.

15. The electrical circuit according to claim 1 , further comprising readout means (RO) for reading out an output signal of said electrical circuit.

16. A one-dimensional or two-dimensional array sensor comprising a plurality of pixels ( 1 . 11 - 1 . nm ),

characterized in that

at least one, and preferably each, of said pixels ( 1 . 11 - 1 . nm ) comprises an electrical circuit according to claim 1 .

17. An apparatus for the demodulation of a modulated signal (I), comprising:

detection means for detecting the modulated signal (I), and evaluation means (EV) for evaluating an envelope amplitude and/or a temporal phase from an output of said detection means,

characterized in that

said detection means comprise an electrical circuit ( 1 . 11 - 1 . nm ) according to claim 1 .

18. The apparatus according to claim 17 , wherein said detection means comprise a plurality of pixels ( 1 . 11 - 1 . nm ) with parallel outputs, at least one, and preferably each, of said pixels ( 1 . 11 - 1 . nm ) comprising said electrical circuit, and wherein said apparatus further comprises at least one on-chip address decoder (CAD. RAD) for individually reading out each electrical circuit ( 1 . 11 - 1 . nm ).

19. A method for the detection of a signal (I) modulated with a modulation frequency, a modulation period being defined as the inverse of the modulation frequency, comprising the steps of:

transducing the modulated signal (I) into an electrical signal,

sampling said electrical signal with a sampling frequency which is equal to four times the modulation frequency or a multiple thereof,

evaluating a plurality of first difference between two samples per modulation period, each separated by half the modulation period, and

evaluating a plurality of second difference between two samples per modulation period, each separated by half the modulation period, said second samples being time-shifted with respect to said first samples by a defined fraction, preferably a quarter, of the modulation period,

characterized in that

a first sum of a plurality of subsequent first differences is evaluated, and

a second sum of a plurality of subsequent second differences is evaluated.

20. The method according to claim 19 , wherein said first and second sum are pre-processed prior to being used for evaluating an envelope amplitude and/or a temporal phase of the modulated signal (I), e.g., a sum of the squares of said first and second sums or a ratio of said first and second sums is calculated.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2006
From: BEER, STEPHAN; SEITZ, PETER
To: CSEM CENTRE SUISSE D'ELECTRONIQUE ET DE MICROTECHNIQUE SA
Reel/Frame 017224/0228 →
Priority Claims (1)
EP 03405164 · Mar 10, 2003 · regional
Continuity (1)
Related Publication 20060097781A1 · May 11, 2006