Circuit arrangement and transistor control method
View Patent ↗In order to improve a circuit arrangement ( 100 ) and a method of controlling at least one transistor ( 10, 12, 14, 18 ), especially of controlling the resistance value of at least one MOS transistor with vanishing DC modulation in such a way that a compensation of resistance variations without control deviation is also possible for the case where the transistor ( 10, 12, 14, 18 ) is operated with a vanishing DC voltage, i.e. with a zero DC voltage and indeed without the aid of a reference frequency, it is suggested that in addition to at least a first reference element ( 10, 20, 70 ), which has at least a first reference transistor ( 10 ) with a first offset from the operating point, at least a second reference element ( 12, 30, 40, 72, 74, 76 ) is provided which has at least a second reference transistor ( 12 ) with a second offset from the operating point equal in value but opposed in sign to the first buffer storage, wherein an in particular arithmetic average can be formed from the first offset and the second offset for approximating and achieving an optimum operating point.
1. A circuit arrangement for controlling the resistance value of at least one MOS transistor with vanishing DC modulation, comprising:
at least one first reference element, which comprises at least one first reference transistor with a first offset from an operating point, and
at least a second reference element, which comprises at least a second reference transistor with a second offset from the operating point equal in value but opposed in sign to the first offset,
wherein an arithmetic mean is taken of the first offset and the second offset for approximating and reaching an optimum operating point.
2. A circuit arrangement as claimed in claim 1 , including:
at least an external resistor by means of which a reference current produces a voltage on the basis of a reference voltage,
the first reference transistor, by means of which a first current corresponding in value and in sign to the reference current produces a first voltage,
at least a first buffer element connected next in line to the drain connection of the first reference transistor or to the source connection of the first reference transistor,
at least a first resistor connected next in line to the output connection of the first buffer element,
at least a second reference transistor by means of which a second current equal but opposed to the first current produces a second voltage,
at least a second buffer element connected to the drain connection of the second reference transistor or to the source connection of the second reference transistor,
at least an operational amplifier, in particular an inverting amplifier with amplification factor−1,
whose first, negative input connection is connected next in line to the output connection of the second buffer element and
whose second, positive input connection is charged with the reference voltage, wherein the second voltage is capable of being inverted to an inverted second voltage with respect to the reference voltage,
at least a second resistor connected next in line to the output connection of the operational amplifier,
at least a comparator element,
whose first, positive input connection is connected next in line to the first resistor and to the second resistor in order to charge this first input connection of the comparator element with a mean voltage averaged over the first resistor and the second resistor, and
whose second, negative input connection is charged with the voltage produced by means of the external resistor, and
at least a condenser element connected next in line to the output connection of the comparator element, which can be charged and discharged by the comparator element as a function of the result of a comparison between the mean voltage value and the voltage produced by the external resistor, wherein the respective gates of the first reference transistor, the second reference transistor and of all further transistors to be controlled, as applicable, can be fed with the voltage of condenser element serving as a control voltage, and wherein the optimum operating point corresponding to the control voltage is reached, the moment the mean voltage value corresponds to the voltage produced by the external resistor.
3. A circuit arrangement as claimed in claim 2 , wherein the source connection of the first reference transistor or the drain connection of the first reference transistor and the source connection of the second reference transistor or the drain connection of the second reference transistor are chargeable with the reference voltage.
4. A circuit arrangement as claimed in claim 2 , wherein the first voltage is lower than the reference voltage and the second voltage is higher than the reference voltage.
5. A circuit arrangement as claimed in claim 2 , wherein, at least a third resistor is connected between the output connection of the second buffer element and the first, negative input connection of the operational amplifier, and at least a fourth resistor is connected parallel to the first, negative input connection of the operational amplifier and to the output connection of the operational amplifier.
6. A method of controlling the resistance value of one or more MOS transistors with vanishing DC modulation, wherein
a first reference transistor produces a positive voltage drop,
a second reference transistor produces a negative voltage drop,
the negative voltage drop is inverted to an inverted voltage drop,
an arithmetic mean voltage value is formed from the positive voltage drop and the inverted voltage drop and is compared with an externally caused voltage drop, and
the resistance values of the first reference transistor, the second reference transistor and all further transistors whose resistance values are to be controlled, as applicable, are regulated by means of a control voltage formed by the comparison of the mean voltage value and the externally caused voltage drop.
7. A device for controlling a resistance value of one or more MOS transistors, comprising:
a first reference element, including a first reference transistor adapted to produce a first voltage less than a reference voltage by a first offset voltage;
a second reference element, including,
a second reference transistor adapted to produce a second voltage greater than the reference voltage by the first offset voltage, and
a circuit adapted to convert the second voltage to a third voltage less than the reference voltage by the first offset voltage;
a resistor adapted to produce a fourth voltage from a voltage drop across the resistor as a result of a reference current passing therethrough;
a comparator adapted to compare the fourth voltage with an arithmetic mean of the first and third voltages; and
a condenser having a terminal connected to an output of the comparator,
wherein the comparator is adapted to charge and discharge a control voltage at the terminal of the condenser in response to the comparison of the fourth voltage and the mean of the first and third voltages, and
wherein the control voltage is provided to a control terminal of each of the one or more MOS transistors whose resistance values are to be controlled, and to control terminals of the first and second reference transistors.