Split-channel antifuse array architecture
Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.
1. An anti-fuse memory array comprising:
a plurality of anti-fuse transistors arranged in rows and columns, each anti-fuse transistor including
a polysilicon gate over a channel region in a substrate, the channel having a preset length;
a diffusion region proximate to a first end of the channel region;
a variable thickness gate oxide between the polysilicon gate and the substrate, the variable thickness gate oxide having a thick gate oxide portion extending from the first end of the channel region to a predetermined distance of the preset length, and a thin gate oxide portion extending from the predetermined distance to a second end of the channel region,
an oxide breakdown zone proximate to the second end of the channel region fusible to form a conductive link between the polysilicon gate and the channel region;
bitlines coupled to the diffusion regions of a column of anti-fuse transistors;
a sense amplifier coupled to a pair of the bitlines through isolation devices, said isolation devices including transistors, each having a gate oxide corresponding to said thick gate oxide portion; and
wordlines coupled to the polysilicon gates of a row of anti-fuse transistors.
2. The anti-fuse memory array of claim 1 , further including wordline decoding circuitry for selectively accessing one anti-fuse transistor coupled to one of the pair of bitlines for a single-ended sensing operation, and for selectively accessing another anti-fuse transistor coupled to the other of the pair of bitlines for a different address.
3. The anti-fuse memory array of claim 1 , further including wordline decoding circuitry for selectively accessing one anti-fuse transistor coupled to one of the pair of bitlines and one anti-fuse transistor coupled to the other of the pair of bitlines for a dual-ended sensing operation.
4. The anti-fuse memory array of claim 1 , further including column select pass gates coupled to the bitlines, at least one of the column select pass gates having a gate oxide corresponding to the thick gate oxide portion.