Method for data signal transfer across different clock-domains
View Patent ↗In a method for data signal transfer across different clock-domains, including synchronization of a data signal with a current clock-domain where said data signal is processed, the processing of said data signal is started before the synchronization of said data signal is completed in said current clock-domain.
1. A method for a first signal transfer across different clock-domains, comprising the acts of:
transferring the first signal from a previous clock domain to a current clock-domain;
receiving a second signal by a first register of the current clock-domain and outputting a semi-synchronized signal;
providing the semi-synchronized signal and a fully synchronized signal to a multiplexer of the current clock-domain for output of a third signal;
receiving by a second register of the current clock-domain the third signal for outputting the fully synchronized signal; and
outputting the first signal synchronized with the current clock-domain using the fully synchronized signal;
wherein outputting the first signal synchronized with the current clock-domain using the fully synchronized signal includes the acts of:
providing the fully synchronized signal to a third register for output of an output signal; and
providing the fully synchronized signal and the output signal to an exclusive OR gate for output of a strobe signal to a further multiplexer for outputting the first signal synchronized with the current clock-domain.
2. An integrated circuit comprising:
a look-up table for transferring first signal from a previous clock domain to a current clock-domain;
a first register of the current clock domain for receiving a second signal and outputting a semi-synchronized signal;
a multiplexer configured to receive the semi-synchronized signal and a fully synchronized signal and output a third signal; and
a second register of the current clock domain for receiving the third signal and outputting the fully synchronized signal.
3. The integrated circuit of claim 2 , further comprising:
a third register configured to receive the fully synchronized signal and provide an output signal; and
an exclusive OR gate configured to receive the fully synchronized signal and the output signal and to output a strobe signal to a further multiplexer for outputting the first signal synchronized with the current clock-domain.
4. The integrated circuit of claim 2 , wherein the semi-synchronized signal comprises an interrupt request signal and the fully synchronized signal comprises an interrupt grant signal.
5. A method for a first signal transfer across different clock-domains, comprising the acts of:
transferring the first signal from a previous clock domain to a current clock-domain;
receiving a second signal by a first register of the current clock-domain and outputting a semi-synchronized signal;
providing the semi-synchronized signal and a fully synchronized signal to a multiplexer of the current clock-domain for output of a third signal; and
receiving by a second register of the current clock-domain the third signal for outputting the fully synchronized signal; and
outputting the first signal synchronized with the current clock-domain using the fully synchronized signal;
wherein the semi-synchronized signal comprises an interrupt request signal and the fully synchronized signal comprises an interrupt grant signal.