Data transfer circuit and flat display device
View Patent ↗The present invention is a data transfer circuit applicable to a liquid crystal display apparatus with a drive circuit formed integrally, for example, on an insulation substrate, and configured such that only an inverted output of a latch result of a first latch section ( 41 ) or only a non-inverted output thereof is data-transferred to a second latch section ( 42 ) and, at least during a period of data transfer to the second latch section ( 42 ), a power supply voltage of the first latch section ( 41 ) is raised.
1. A data transfer circuit comprising:
a first latch section that latches an input data inputted to said first latch section, and outputs a single-phase first latch result obtained by latching said input data; and
a second latch section that latches said single-phase first latch result outputted from said first latch section,
wherein said first latch section includes a first inverter and a second inverter, an input from said first inverter being inputted to said second inverter via a switching circuit,
wherein a first power supply voltage of said first latch section is set to a first voltage or a second voltage that is different from said first voltage, and a second power supply voltage of said second latch section is set to said second voltage,
wherein said first power supply voltage of said first latch section is set to said first voltage when the input data inputted and latched in the first latch section, and set to said second voltage while said single-phase first latch result is transferred to said second latch section, and
wherein said single phase first latch result is an inverted output of the first latch result.
2. The data transfer circuit according to claim 1 , wherein said second voltage is higher than said first voltage.
3. The data transfer circuit according to claim 1 , wherein said second voltage is sufficient to prevent a voltage drop due to the transfer of said single-phase first latch result to said second latch section.
4. The data transfer circuit according to claim 1 , wherein said second voltage is 5.8 V.
5. The data transfer circuit according to claim 1 , wherein said second voltage is at least 2.9 V greater than said first voltage.
6. The data transfer circuit according to claim 1 , wherein said first latch section latches gradation data.
7. The data transfer circuit according to claim 1 , wherein said first and second inverters are arranged in parallel between said first power supply voltage and a first negative power supply.
8. The data transfer circuit according to claim 7 , wherein said input data is inputted to said first inverter.
9. The data transfer circuit according to claim 1 , wherein said switching circuit operates off-action at a sampling pulse.
10. The data transfer circuit according to claim 9 , wherein said input data is inputted to said first inverter via a transistor that operates on-action at said sampling pulse.
11. The data transfer circuit according to claim 1 , wherein a transfer switch is arranged between said first latch section and said second latch section, an output of said transfer switch being supplied to said second latch section.
12. The data transfer circuit according to claim 1 , wherein said second latch section further comprises a third inverter and a fourth inverter, said third and fourth inverters arranged in parallel between said second power supply voltage and a second negative power supply.
13. The data transfer circuit according to claim 12 , wherein said first latch result is inputted to said third inverter.
14. The data transfer circuit according to claim 12 , wherein said second latch section level shifts said transfer circuit output by setting-up said second negative power supply.
15. The data transfer circuit according to claim 1 , wherein said power supply voltage of said first latch section is raised from said first voltage to said second voltage before said single-phase first latch result is transferred to said second latch section.
16. The data transfer circuit according to claim 1 , wherein said single phase first latch result is a non-inverted output of the first latch result.
17. The data transfer circuit according to claim 16 , wherein said power supply voltage of said first latch section is raised from said first voltage to said second voltage before said single-phase first latch result is transferred to said second latch section.
18. The data transfer circuit according to claim 17 , wherein said second voltage is sufficient to prevent a voltage drop due to the transfer of said single-phase first latch result to said second latch section.
19. The data transfer circuit according to claim 1 , wherein said input data inputted to said first inverter via a switching element,
while said input data is inputted, said switching element is set to an on-state and said switching circuit is set to an off-state, and
after the inputting of said input data is finished, said switching element is set to an off-state and said switching circuit is set to an on-state.
20. The data transfer circuit according to claim 19 , wherein said second voltage is higher than said first voltage.