Video signal processing circuit, control method of video signal processing circuit, and integrated circuit
View Patent ↗A display error occurs upon contention between writing of pixel data in a GRAM and reading of pixel data representing a scanning line including pixels which correspond to the pixel data above. Pixel data corresponding to pixels representing a scanning line stored in a latch circuit is displayed on a display panel, and when contention occurs between writing of pixel data in a GRAM and reading of pixel data corresponding to pixels representing a scanning line to the latch circuit from the GRAM, a controller delays reading of the pixel data corresponding to the pixels representing the scanning line and controls so as to perform reading of the pixel data corresponding to the pixels representing the scanning line to the latch circuit from the GRAM once again.
1. A video signal processing circuit, comprising:
a GRAM which stores pixel data, which is data corresponding to pixels of a display screen, at least in the amount equivalent to said display screen, said pixel data being written in said GRAM in synchronization to a memory clock signal;
a latch circuit which reads and stores pixel data corresponding to pixels representing a scanning line of said display screen from said GRAM; and
a control unit,
wherein said pixel data corresponding to said pixels representing said scanning line stored in said latch circuit is displayed on said display screen,
in the case of contention between writing of said pixel data in said GRAM and reading of said pixel data corresponding to said pixels representing said scanning line to said latch circuit from said GRAM, said control unit delays for a predetermined delay time reading of said pixel data corresponding to said pixels representing said scanning line and controls so as to perform reading of said pixel data corresponding to said pixels representing said scanning line to said latch circuit from said GRAM once again, and
said control unit comprises a delay unit which delays and inputs a display read control signal and a data latch signal for said predetermined delay time during a period which is after a point at which said memory clock signal corresponding to writing of said pixel data in said GRAM is supplied, said writing accompanying said contention, but which is before supplying of the next memory clock signal following said memory clock signal so that said latch circuit reads pixel data corresponding to pixels representing said scanning line.
2. The video signal processing circuit of claim 1 , wherein said predetermined delay time can be adjusted in a variable manner.
3. The video signal processing circuit of claim 1 , wherein said control unit comprises a monitoring unit which monitors whether writing of said pixel data in said GRAM contends against reading of said pixel data corresponding to said pixels representing said scanning line to said latch circuit from said GRAM.
4. The video signal processing circuit of claim 3 , wherein said control unit comprises a delay unit which delays reading of said pixel data corresponding to said pixels representing said scanning line based on a monitoring result obtained by said monitoring unit and controls so as to perform reading of said pixel data corresponding to said pixels representing said scanning line to said latch circuit from said GRAM once again.
5. A video signal processing circuit, comprising:
a GRAM which stores pixel data, which is data corresponding to pixels of a display screen, at least in the amount equivalent to said display screen, said pixel data being written in said GRAM in synchronization to a memory clock signal;
a latch circuit which reads and stores pixel data corresponding to pixels representing a scanning line of said display screen from said GRAM; and
a control unit,
wherein said pixel data corresponding to said pixels representing said scanning line stored in said latch circuit is displayed on said display screen,
in the case of contention between writing of said pixel data in said GRAM and reading of said pixel data corresponding to said pixels representing said scanning line to said latch circuit from said GRAM, said control unit delays for a predetermined delay time reading of said pixel data corresponding to said pixels representing said scanning line and controls so as to perform reading of said pixel data corresponding to said pixels representing said scanning line to said latch circuit from said GRAM once again, and
when writing of said pixel data in said GRAM is executed plural times during a contention-free memory update period in which said pixel data corresponding to said pixels representing said scanning line are read to said latch circuit from said GRAM said control unit upon occurrence of said contention delays reading of said pixel data corresponding to said pixels representing said scanning line between a period of writing said pixel data and a period of writing next pixel data, and controls so as to perform reading of said pixel data corresponding to said pixels representing said scanning line to said latch circuit from said GRAM again plural times during said contention-free memory update period.