IP Library Granted Patent US 7,696,989
Granted Patent B2
US 7,696,989 · App. 10/563,298 · Granted Apr 13, 2010

Flat display apparatus and integrated circuit

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Quick Facts
Patent No.
US 7,696,989
App. No.
10/563,298
Granted
Apr 13, 2010
Kind
B2
Abstract

The present invention is applied, for example, to a liquid crystal display apparatus in which drive circuitry is formed integrally on an insulating substrate, wherein processing results from circuit blocks 41 A, 41 B on the side of a higher power supply voltage are inputted into the side of a lower power supply voltage through active elements performing on-off operation complementarily, and by the fall of the power supply voltage on this higher side, the output of these active elements is set to a predetermined level.

Claims (18)

1. A flat display apparatus in which a display unit formed by arranging pixels in a matrix and a drive circuit driving the display unit are formed integrally on a substrate, characterized in that:

the drive circuit has a first circuit block operating by a first power supply voltage and a second circuit block operating by a second power supply voltage, which is lower than the first power supply voltage, for processing a processing result by the first circuit block;

the second circuit block receives an input of the processing result of the first circuit block at an active element performing on-off operation complementarily; and

the first circuit block has a level setting circuit for setting a level of the processing result so as to hold an output of the active element at a predetermined level by a fall of the first power supply voltage,

the first circuit block has a first inverter operating by the first power supply voltage, a second inverter for outputting the processing result based on the output of the first inverter to the second circuit block, and a power supply switching circuit for switching a power supply voltage of the second inverter from the first power supply voltage to the second power supply voltage by a fall of the first power supply; and

the level setting circuit holds the output of the active element at a predetermined level by setting of an input level of the second inverter.

2. The flat display apparatus according to claim 1 , characterized in that:

the second circuit block is a reference voltage generating circuit for generating a plurality of reference voltages by resistively dividing a reference voltage by a resistance block, and a reference voltage selector for selectively outputting the plurality of reference voltages according to gradation data showing gradation of the pixels; and

the active element performing on-off operation complementarily is an active element of a switch circuit for switching a polarity of the generated reference voltage by outputting the output to the resistance block to switch a terminal voltage of the resistance block according to the processing result.

3. The flat display apparatus according to claim 1 , characterized in that:

the second circuit block is a drive circuit for switching electrode potential of a storage capacitor provided in each of the pixels; and

the active element performing on-off operation complementarily is an active element for outputting the output to the storage capacitor to switch the electrode potential according to the one processing result.

4. The flat display apparatus according to claim 1 , characterized in that:

the second circuit block is a drive circuit for switching electrode potential of liquid crystal cells of the pixels; and

the active element performing on-off operation complementarily is an active element for outputting the output to the liquid crystal cells to switch the electrode potential according to the processing result.

5. The flat display apparatus according to claim 1 , characterized by comprising:

a power supply circuit for generating a power supply by the first power supply voltage from a power supply by the second power supply voltage, wherein

the power supply by the second power supply voltage is supplied externally.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
CHANGE OF NAME Recorded Oct 28, 2015
From: JAPAN DISPLAY WEST INC.
To: JAPAN DISPLAY INC.
Reel/Frame 036985/0524 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2013
From: SONY CORPORATION
To: JAPAN DISPLAY WEST INC.
Reel/Frame 031377/0874 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2006
From: KIDA, YOSHITOSHI; NAKAJIMA, YOSHIHARU
To: SONY CORPORATION
Reel/Frame 017437/0288 →