Integrated data processing circuit with a plurality of programmable processors
An integrated data processing circuit contains matrix of programmable processors. Each processor ( 12 ) has private operand transfer connections to its neighboring processors ( 12 ) in the matrix, typically for passing operands of transfer commands. An additional tree communication structure contain router circuits ( 16, 18, 19 ) hierarchically coupled to each other and to the processors. The processors ( 12 ) form leave nodes of the tree structure, the router circuits ( 16, 18, 19 ) being arranged to route a message with an address from a root router ( 19 ) circuit to an addressed processor ( 12 ), selectively via a path through the tree structure, the router circuits ( 16, 18, 19 ) each selecting a part of the path under control of the address.
1 . An integrated data processing circuit comprising:
programmable processors arranged in a two-dimensional matrix, each processor having private operand transfer connections to its neighboring processors in the matrix;
a communication structure comprising router circuits hierarchically coupled to each other and to the processors in a tree structure, the processors forming leave nodes of the tree structure, the router circuits being arranged to route a message with an address from a root router circuit to an addressed processor, selectively via a path through the tree structure, the router circuits each selecting a part of the path under control of the address.
2 . An integrated data processing circuit according to claim 1 , the processors each supporting a command to transfer an operand of said command via a selected one of the private operand transfer connections.
3 . A data processing circuit according to claim 1 , wherein the address contains a plurality of bits, each router circuit being arranged to select a slice of the bits, the router circuits controlling routing to direct successor router circuits and/or processors in the tree structure dependent on the bits in the slice only, successive router circuits along each path from the root router circuit to a respective processor each selecting a different slice.
4 . A data processing circuit according to claim 1 , wherein each particular router circuit is associated with a region in the matrix, which contain those of the processors that are coupled directly or indirectly to the particular router circuit through the tree structure, a hierarchically higher region associated with any hierarchically higher router circuit being divided into spatially separate successor regions of hierarchically lower router circuits directly connected to the hierarchically higher router circuit.
5 . A data processing circuit according to claim 4 , wherein the tree structure forms a quadtree, each router circuit being coupled to four hierarchically lower router circuits and/or processors dividing the higher region into four quadrants associated with respective ones of the four hierarchically lower router circuits and/or processors.
6 . A data processing circuit according to claim 5 , wherein the address contains a plurality of bits, each router circuit being arranged to select a slice of two of the bits, the router circuits controlling routing to direct successor router circuits and/or processors in the tree structure dependent on the bits in the slice only, successive router circuits along each path from the root router circuit to a respective processor each selecting a different slice.
7 . A data processing circuit according to claim 1 , wherein the router circuits are furthermore arranged to route a further message with a further address of a particular first one of the processors from a particular second one of the processors via a first sub-path through the tree structure in a first direction towards the root router circuit until the further message reaches a router circuit that serves the addressed first one of the processors, subsequently crossing over to transmission via a second sub-path through the tree structure towards the first one of the processors the router circuits selecting the first and second sub-path under control of the further address,
8 . A data processing circuit according to claim 7 , the data processing circuit comprising arbiter circuits each associated with a respective one of the router circuits arranged to arbitrate a collision between the message from the root router circuit and the further message upon cross over.
9 . A data processing circuit according to claim 8 , wherein the arbiter circuits are arranged to arbitrate a collision between the further messages from different ones of the processors.
10 . A data processing circuit according to claim 1 , comprising a common control unit, arranged to send a parameter for use in processing to a selected one of the processors in the message.
11 . A method of manufacturing an integrated circuit, the method comprising:
selecting dimensions of a two dimensional matrix of processors;
generating instructions to layout the processors in the matrix with a design computer;
generating instructions to layout private operand transfer connections between pairs of neighboring processors in the matrix with the design computer;
automatically generating instructions with the design computer to layout router circuits hierarchically coupled to each other and to the processors in a tree structure, the processors forming leave nodes of the tree structure, the router circuits being arranged to route a message with an address from a root router circuit to an addressed processor selectively via a path through the tree structure, the router circuits each selecting a part of the path under control of the address, the design computer selecting a number of levels of router circuits in the tree structure;
manufacturing the integrated circuit according to the generated layout.