Radiation-emitting thin-film semiconductor chip

1. A radiation-emitting thin-film semiconductor chip comprising an epitaxial multilayer structure, a carrier substrate and a reflective layer or interface, the epitaxial multilayer structure comprising:

an active, radiation-generating layer,

a first main face, and

a second main face remote from the first main face for coupling out the radiation generated in the active, radiation-generating layer,

wherein the first main face of the multilayer structure is coupled to the reflective layer or interface, and

wherein a patterned region of the multilayer structure that adjoins the second main face of the multilayer structure is patterned by either one- or two-dimensional depressions forming convex elevations, each said convex elevation having an upper surface that is not contiguous with an upper surface of an adjacent elevation,

wherein the epitaxial multilayer structure is based on one of an arsenide compound semiconductor material and GaN,

wherein the depressions of the patterned region are formed in said epitaxially grown semiconductor material of the multilayer structure,

wherein the reflective layer is located between the carrier substrate and the epitaxial multilayer structure, and

wherein the reflective layer is formed as a metallic contact layer.

2. The semiconductor chip as claimed in claim 1 , wherein the epitaxial multilayer structure of the semiconductor chip is free of a growth substrate.

3. The semiconductor chip as claimed in claim 1 , wherein the elevations have a form of truncated pyramids or truncated cones or a trapezoidal cross-sectional form.

4. The semiconductor chip as claimed in claim 1 , wherein the elevations have a form of cones or a triangular cross-sectional form.

5. The semiconductor chip as claimed in claim 1 , wherein the elevations have an inclination angle (β) of between approximately 40° and approximately 50°.

6. The semiconductor chip as claimed in claim 1 , wherein the elevations have a height (h 1 ) at least as large as a distance (h 2 ) between the patterned region and the active, radiation-generating layer.

7. The semiconductor chip as claimed in claim 6 , wherein the height (h 1 ) of the elevations is approximately twice as large as the distance (h 2 ) between the patterned region and the active, radiation-generating layer.

8. The semiconductor chip as claimed in claim 1 , wherein a cell size (d) of the elevations is at most approximately five times as large as a height (h 1 ) of the elevations.

9. The semiconductor chip as claimed in claim 8 , wherein the cell size (d) of the elevations is at most approximately three times as large as the height (h 1 ) of the elevations.

10. The semiconductor chip as claimed in claim 1 , wherein the reflective layer or interface coupled to the first main area of the multilayer structure has a reflectivity of at least 85%.

11. The semiconductor chip as claimed in claim 2 , wherein the multilayer structure is applied onto the carrier substrate either directly by the first main face or via the reflective layer or interface.

12. The semiconductor chip as claimed in claim 11 , wherein the reflective layer or interface or the carrier substrate serves as a contact layer of the semiconductor chip.

13. The semiconductor chip as claimed in claim 1 , further comprising a conductive, transparent layer applied onto the second main face of the multilayer structure.

14. The semiconductor chip as claimed in claim 1 , further comprising a transparent protective layer applied onto the second main face of the multilayer structure.

15. The semiconductor chip as claimed in claim 1 , wherein the multilayer structure comprises a material or a plurality of different materials based on GaN.

16. The semiconductor chip as claimed in claim 1 , wherein the second main face is a noncontinuous layer.

17. The semiconductor chip as claimed in claim 1 , wherein the reflective layer is in direct contact with the epitaxial multilayer structure.

18. The semiconductor chip as claimed in claim 1 , wherein the epitaxial multilayer structure is based on a II-VI semiconductor material.

19. The semiconductor chip as claimed in claim 1 , wherein the epitaxial multilayer structure is based on a phosphide compound semiconductor material.

20. The semiconductor chip as claimed in claim 1 , wherein the epitaxial multilayer structure is based on an arsenide compound semiconductor material.

21. The semiconductor chip as claimed in claim 1 , wherein the patterned region of the multilayer structure that adjoins the second main face of the multilayer structure is patterned by two-dimensional depressions forming convex elevations.

22. The semiconductor chip as claimed in claim 1 , wherein the convex elevations have an inclination angle (β) of between approximately 30° and approximately 70°.

23. The semiconductor chip as claimed in claim 22 , wherein the elevations have an inclination angle (β) of between approximately 40° and approximately 50°.

24. A radiation-emitting thin-film semiconductor chip comprising an epitaxial multilayer structure, a carrier substrate and a reflective layer or interface, the epitaxial multilayer structure comprising:

an active, radiation-generating layer,

a first main face, and

a second main face remote from the first main face for coupling out the radiation generated in the active, radiation-generating layer,

wherein the first main face of the multilayer structure is coupled to the reflective layer or interface,

wherein a patterned region of the multilayer structure that adjoins the second main face of the multilayer structure is patterned by either one- or two-dimensional depressions forming convex elevations, each said convex elevation having an upper surface that is not contiguous with an upper surface of an adjacent elevation,

wherein the epitaxial multilayer structure is based on one of an arsenide compound semiconductor material and GaN,

wherein the depressions of the patterned region are formed in said epitaxially grown semiconductor material of the multilayer structure,

wherein the reflective layer is located between the carrier substrate and the epitaxial multilayer structure,

wherein the reflective layer is formed as a metallic contact layer, and

wherein the carrier substrate comprises sapphire or silicon.