A charge pump comprises a single voltage multiplier stage ( 1 ) which converts an input voltage (VDD) into an output voltage (Vo) under control of a clock signal (Q, Qn; CLKO). An oscillator ( 2 ) receives the input voltage (VDD) to generate the clock signal (Q, Qn; CLKO) having a repetition period (Tr 1 , Tr 2 ) which is substantially proportional to a squared input voltage (VDD 2 ).
1. A charge pump comprising:
a single voltage multiplier stage ( 1 ) for converting an input voltage (VDD) into an output voltage (Vo) under control of a clock signal (Q, Qn; CLKO), and
an oscillator ( 2 ) for receiving the input voltage (VDD) to generate the clock signal (Q, Qn; CLKO) having a repetition period (Tr 1 , Tr 2 ) being substantially proportional to a squared input voltage (VDD 2 ).
2. A charge pump as claimed in claim 1 , wherein the oscillator ( 2 ) comprises:
a control circuit (CC) for receiving the input voltage (VDD) to supply a control signal (CS) being substantially proportional to the squared input voltage (VDD 2 ), and wherein the repetition period of the oscillator ( 2 ) is substantially linearly dependent on the control signal (CS).
3. A charge pump as claimed in claim 1 , wherein the oscillator ( 2 ) comprises:
a capacitor (MP 13 , MP 14 ),
a current source (MN 7 ) for supplying a current (Io) to charge or discharge the capacitor (MP 13 , MP 14 ),
a control circuit (MP 1 ) for receiving the input voltage (VDD) to supply a further current ( 1 d ) being substantially proportional to the squared input voltage (VDD 2 ), wherein the first mentioned current (Io) and the further current ( 1 d ) have a fixed ratio.
4. A charge pump as claimed in claim 1 , wherein the charge pump further comprises a duty cycle modulator ( 3 ) for modulating a duty cycle of the clock signal (CLKO), the duty cycle modulator ( 3 ) comprises an input for receiving the output voltage (Vo) to adapt the duty cycle to obtain a substantially constant output voltage (Vo).
5. A charge pump as claimed in claim 4 , wherein the duty cycle modulator ( 3 ) comprises:
a first comparator (COM 1 ) for comparing the output voltage (Vo) with a reference voltage (Vr) to supply a comparison signal (COS),
a first integrator (C 2 ) for generating a first saw-tooth signal (CPO) having a rising or falling slope dependent on whether the comparison signal (COS) indicates that the output voltage (Vo) is above or below the reference voltage (Vr), or the other way around,
a second integrator (C 3 ) for generating a second saw-tooth signal (RA) having a slope dependent on the squared input voltage (VDD 2 ), and
a second comparator (COM 2 ) for comparing the first saw-tooth signal (CPO) and the second saw-tooth signal (RA), the duty cycle being dependent on an instant the first saw-tooth signal (CPO) reaches the second saw-tooth signal (RA).
6. An integrated circuit for use in a charge pump comprising a single voltage multiplier stage ( 1 ) for converting an input voltage (VDD) into an output voltage (Vo) under control of a clock signal (Q, Qn; CLKO), the integrated circuit comprising:
an oscillator ( 2 ) for receiving the input voltage (VDD) to generate the clock signal (Q, Qn; CLKO) having a repetition period (Tr 1 , Tr 2 ) being substantially proportional to a squared input voltage (VDD 2 ).
7. A mobile device having a charge pump comprising:
a single voltage multiplier stage ( 1 ) for converting an input voltage (VDD) supplied by a battery into an output voltage (Vo) under control of a clock signal (Q, Qn; CLKO), and
an oscillator ( 2 ) for receiving the input voltage (VDD) to generate the clock signal (Q, Qn; CLKO) having a repetition period (Tr 1 , Tr 2 ) being substantially proportional to a squared input voltage (VDD 2 ).
8. A USB master device having a charge pump comprising:
a single voltage multiplier stage ( 1 ) for converting an input voltage (VDD) into an output voltage (Vo) for a USB slave device under control of a clock signal (Q, Qn; CLKO), and
an oscillator ( 2 ) for receiving the input voltage (VDD) to generate the clock signal (Q, Qn; CLKO) having a repetition period (Tr 1 , Tr 2 ) being substantially proportional to a squared input voltage (VDD 2 ).