Receiver and electronic device using the same
View Patent ↗A receiver and an electronic device are provided that suppress deterioration of the signal waveform of a symbol. The receiver has a filter that sends out an output signal having a symbol at an arbitrary time interval; and an intermittent operation part that controls the filter intermittently at an arbitrary time interval, according to an output signal supplied from the filter. This arrangement prevents deterioration of the signal waveform of a symbol, by setting the timing for switching the signal for controlling the frequency characteristic of the filter, to an arbitrary period between symbol periods such as a guard interval.
1. A receiver comprising:
a filter that sends out an output signal having a symbol at an arbitrary time interval;
an intermittent operation part that controls the filter intermittently at the time interval, according to the output signal supplied from the filter; and
a timing signal generator that generates a timing signal for turning on and off a power supply of the intermittent operation part, according to the arbitrary time interval in the output signal supplied from the filter.
2. The receiver as claimed in claim 1 , wherein the timing signal generator generates a timing signal for turning on and off the power supply of the intermittent operation part, according to the control signal from the intermittent operation part.
3. The receiver as claimed in claim 2 , wherein the timing signal generator generates a timing signal for turning on and off the power supply of the intermittent operation part, according to a control signal from the intermittent operation part and an off period of the power supply of the intermittent operation part.
4. The receiver as claimed in claim 1 , wherein the timing signal generator generates a timing signal for turning on and off the power supply of the intermittent operation part, according to signal strength of the control signal from the intermittent operation part.
5. The receiver as claimed in claim 4 , wherein the timing signal generator generates a timing signal for turning on and off the power supply of the intermittent operation part, according to a control signal from the intermittent operation part and an off period of the power supply of the intermittent operation part.
6. The receiver as claimed in claim 1 , wherein the timing signal generator generates a timing signal for turning on and off the power supply of the intermittent operation part, according to a reference clock in addition to the arbitrary time interval in the output signal.
7. An electronic device loaded with the receiver as claimed in claim 1 .
8. A receiver comprising:
a filter that sends out an output signal having a symbol at an arbitrary time interval;
an intermittent operation part that controls the filter intermittently at the time interval, according to the output signal supplied from the filter; and
a register that holds a control signal from the intermittent operation part,
wherein the filter is controlled according to the control signal held by the register.
9. An electronic device loaded with the receiver as claimed in claim 8 .
10. A frequency adjusting circuit comprising:
a reference filter that sets a phase difference to a reference clock signal;
a multiplication circuit that multiplies the output signal supplied from the reference filter by the reference clock signal;
a low-pass filter that is connected to an output of the multiplication circuit, the frequency adjusting circuit providing the reference filter with an output voltage supplied from the low-pass filter, to provide the reference filter with negative feedback, so that a cutoff frequency of the reference filter remains constant;
a sample hold circuit that holds an output voltage supplied from the low-pass filter for a constant period;
an analog-to-digital converter that converts an output voltage supplied from the sample hold circuit to digital data;
a digital-to-analog converter that converts the digital data to an analog adjusted value; and
a register that holds the digital data converted, wherein the frequency adjusting circuit is operated intermittently according to the digital data held by the register.