Testing of embedded systems

1. A method of testing at least one embedded device under test (DUT) comprising:

determining a test configuration parameter set comprising predefined DUT test sequence rules;

determining a first data set comprising input test vectors based on the test configuration parameter set;

processing the first data set in a DUT model to determine output test vectors wherein the output test vectors comprise DUT model generated responses to the input test vectors;

processing the first data set and the output test vectors, comprising:

parsing the output test vectors with the first data set in accordance with a predefined timing reference in which the predefined timing reference determines a point in time to sample an output test vector as a stabilised output test vector; and

matching each stabilised output test vector to form pairs of stabilised input and output test vectors to determine a second data set comprising pairs of stabilised input and output test vectors;

communicating the stabilised input test vectors to at least one DUT via a DUT independent interface so that the at least one DUT is stimulated by the stabilised input test vectors to produce DUT output vectors;

determining a third data set comprising the stabilised input vectors and corresponding DUT output vectors; and

comparing the third data set with the second data set to determine a comparison of actual behaviour to modelled behaviour of the at least one DUT;

wherein the predefined timing reference is derived from a logical connection port adapted to indicate a predefined timing reference for determining a point in time at which to sample an output vector as the corresponding output vector in an input/output vector pair.

2. The method of claim 1 wherein the DUT independent interface comprises an interprocess communication protocol utilising one of:

TCP/IP;

Active-X; and

a serial communications standard.

3. The method of claim 1 wherein the DUT model comprises at least one of the following abstraction techniques:

architectural level descriptions;

data type definitions;

state transition diagrams; and

extended Message Sequence Charts.

4. The method of claim 1 wherein the data set comprises test vector formatted files.

5. The method of claim 1 wherein the test configuration parameter set comprises a test parameter configuration file.

6. The method of claim 1 wherein the DUT comprises at least one of:

a smoke detector;

a fire detector;

a security device;

a medical device;

a biological tissue processing device; and

an industrial process device.

7. A computer-readable medium storing thereon a computer program comprising a set of instructions operable to cause a processor to perform the following operations, the operations comprising:

determine a test configuration parameter set comprising predefined device under test (DUT) test sequence rules;

determine a first data set comprising input test vectors based on the test configuration parameter set;

process the first data set in a DUT model to determine output test vectors wherein the output test vectors comprise DUT model generated responses to the input test vectors;

process the first data set and the output test vectors, comprising:

parsing the output test vectors with the first data set in accordance with a predefined timing reference in which the predefined timing reference determines a point in time to sample an output test vector as a stabilised output test vector; and

matching each stabilised output test vector to form pairs of stabilised input and output test vectors to determine a second data set comprising pairs of stabilised input and output test vectors;

communicate the stabilised input test vectors to at least one DUT via a DUT independent interface so that the at least one DUT is stimulated by the stabilised input test vectors to produce DUT output vectors;

determine a third data set comprising the stabilised input vectors and corresponding DUT output vectors; and

compare the third data set with the second data set to determine a comparison of actual behaviour to modelled behaviour of the at least one DUT;

wherein the predefined timing reference is derived from a logical connection port adapted to indicate a predefined timing reference to determine a point in time at which to sample an output vector as the corresponding output vector in an input/output vector pair.