IP Library Granted Patent US 7,894,333
Granted Patent B2
US 7,894,333 · App. 10/593,882 · Granted Feb 22, 2011

Method and apparatus for use in carrier recovery in a communications system

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Quick Facts
Patent No.
US 7,894,333
App. No.
10/593,882
Granted
Feb 22, 2011
Kind
B2
Abstract

A receiver includes a digital phase locked loop (PLL) for performing carrier recovery. The digital PLL further includes a phase error estimator driven by hard decisions and an integrator, which accumulates a phase error signal provided by the phase error estimator. To reduce the acquisition time, the digital PLL is run in an open-loop mode during which an estimate of the carrier frequency offset is determined as a function of the phase error signal. After the estimate of the carrier frequency offset is determined, the integrator is pre-loaded with the determined estimate and the digital PLL is run in a closed-loop mode.

Claims (17)

1. A method for use in a receiver, the method comprising:

using the receiver to perform the steps of

processing a received signal with a phase-locked loop (PLL);

generating a carrier frequency offset estimate as a function of a phase error signal of the PLL; and

detecting a false lock condition as a function of comparing the carrier frequency offset estimate to a closed loop value of the PLL.

2. The method of claim 1 , wherein the processing step includes the step of setting the PLL in an open loop mode of operation.

3. The method of claim 1 , wherein the generating step includes the steps of:

determining a rollover count value for the phase error signal;

determining a symbol count value of the received signal; and

generating the carrier frequency offset estimate from the determined rollover count value and determined symbol count value.

4. The method of claim 1 , further comprising the step of updating the PLL with the carrier frequency offset estimate.

5. A receiver comprising:

a carrier tracking loop (CTL) for processing a received signal; and

a processor for estimating a carrier frequency offset as a function of a phase error signal of the CTL;

wherein the processor detects a false lock condition as a function of comparing the estimate of the carrier frequency offset to a closed loop value of the CTL.

6. The receiver of claim 5 , wherein the CTL includes a rollover counter and a symbol counter accessible by the processor for use in estimating the carrier frequency offset.

7. The receiver of claim 5 , wherein the receiver is a set-top box.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2018
From: THOMSON LICENSING DTV
To: INTERDIGITAL MADISON PATENT HOLDINGS
Reel/Frame 046763/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2017
From: THOMSON LICENSING
To: THOMSON LICENSING DTV
Reel/Frame 043302/0965 →
CHANGE OF NAME Recorded Apr 21, 2017
From: THOMSON LICENSING S.A.
To: THOMSON LICENSING
Reel/Frame 042303/0268 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2008
From: BELOTSERKOVSKY, MAXIM B.
To: THOMSON LICENSING S.A.
Reel/Frame 020677/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2006
From: THOMSON LICENSING S.A.
To: THOMSON LICENSING
Reel/Frame 018355/0901 →