Sea-of-cells array of transistors
View Patent ↗The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.
1. An integrated circuit, comprising:
a logic inverter comprising:
an n-channel field effect transistor;
a p-channel field effect transistor;
a gate, common to both said n-channel field effect transistor and said p-channel field effect transistor, wherein said gate is formed in a layer of polysilicon; and
a connection between a drain of the p-channel field effect transistor and a drain of the n-channel field effect transistor formed in said same layer of polysilicon, wherein the polysilicon comprising said gate is coplanar with the polysilicon comprising said connection between said drain of the p-channel field effect transistor and said drain of the n-channel field effect transistor.
2. The integrated circuit as described in claim 1 , further comprising:
a first layer of metallization; and
a second layer of metallization, wherein the second layer of metallization comprises substantially no local interconnect.
3. The integrated circuit as described in claim 2 , wherein said second layer of metallization comprises no local interconnect.
4. The integrated circuit as described in claim 1 , further comprising:
a plurality of MACROs;
a first first layer of metallization; and
a second layer of metallization interconnecting said plurality of MACROs.
5. The integrated circuit as described in claim 4 , further comprising, no local interconnect within said second layer of metallization in at least one of said MACROs.
6. The integrated circuit as described in claim 4 , further comprising, no local interconnect within said second layer of metallization in a plurality of said MACROs.
7. The integrated circuit as described in claim 4 , further comprising, no local interconnect within said second layer of metallization in all of said plurality of MACROs.
8. The integrated circuit as described in claim 4 , wherein at least one of said MACROs is comprised by a standard cell array of the integrated circuit.
9. The integrated circuit as described in claim 8 , wherein said standard cell array comprises a row pitch and at least one MACRO has a row pitch equivalent to the row pitch of said standard cell array.