Photonic sigma delta analog-to-digital conversation employing dual heterojunction thyristors
View Patent ↗Interference caused by the propagation of a transmit signal transmitted from a transmit antenna to a receive antenna is effectively cancelled by an improved signal cancellation system. The system includes an interference cancellation signal generator that generates a time-delayed and amplitude-reduced representation of said transmit signal. A summing stage is operably coupled to the interference cancellation signal generator and the receive antenna. The summing stage subtracts the time-delayed and amplitude-reduced representation of the transmit signal from a receive signal to substantially cancel the interference. The interference cancellation signal generator preferably includes a novel programmable optical delay line that introduces a variable amount of optical delay to an optical signal derived from said transmit signal in addition to a thyristor-based sigma delta modulator that converts samples of the transmit signal to into a digital signal in the optical domain.
1. A sigma-delta-type analog-to-digital converter comprising:
an integration stage comprising a resistor, a first heterojunction thyristor device, and a feedback capacitor, wherein said first heterojunction thyristor has an input terminal and an output terminal, said input terminal operably coupled to said resistor, said feedback capacitor operably coupled between said input terminal and said output terminal, and said first heterojunction thyristor providing high gain amplification of an electrical signal communicated between said input terminal and said output terminal; and
a second heterojunction thyristor device adapted to contemporaneously perform 1-bit analog-to-digital conversion and electrical-to-optical conversion of the result of the 1-bit analog-to-digital conversion.
2. A sigma-delta-type analog-to-digital converter according to claim 1 , wherein:
said first heterojunction thyristor device includes a injector terminal electrically coupled to a quantum well channel, a bias current source operably coupled to said injector terminal to provide a desired switching voltage having high gain characteristics, and bias resistance that sets a bias current through said first heterojunction device at a point corresponding to said desired switching voltage.
3. A sigma-delta-type analog-to-digital converter according to claim 1 , further comprising:
a current source and a third heterojunction transistor that operate in response to a sampling clock signal supplied thereto to reset said second heterojunction thyristor when a sampling period defined by said sampling clock signal has ended.
4. A sigma-delta-type analog-to-digital converter according to claim 3 , wherein:
said sampling clock signal comprises one of an electrical clock signal and optical clock signal.
5. A sigma-delta-type analog-to-digital converter according to claim 1 , further comprising:
another heterojunction thyristor adapted to operated as a 1-bit DAC in accordance with an output signal produced by said second heterojunction thyristor.
6. A sigma-delta-type analog-to-digital converter according to claim 5 , wherein:
said output signal comprises one of an electrical signal and optical signal representing results of said 1-bit analog-to-digital conversion performed by said second heterojunction thyristor.
7. A sigma-delta-type analog-to-digital converter according to claim 1 , further comprising:
a decimation circuit operably coupled to electrical output of said second heterojunction thyristor device.
8. A sigma-delta-type analog-to-digital converter according to claim 1 , wherein:
all of said electronic and optoelectronic circuit elements that realize said sigma-delta converter are formed from a common inversion quantum-well channel device structure.