Complex multiplication method and apparatus with phase rotation

1. A method of complex multiplication comprising steps of:

(a) receiving a complex multiplicand having a real value and an imaginary value;

(b) generating a negation of the real value of the complex multiplicand;

(c) generating a negation of the imaginary value of the complex multiplicand;

(d) receiving a complex multiplier; and

(e) selecting a phasor constant having a value wherein a complex product of the complex multiplicand times the complex multiplier times the phasor constant has a real value equal to one of the real value of the complex multiplicand, the imaginary value of the complex multiplicand, the negation of the real value of the complex multiplicand, and the negation of the imaginary value of the complex multiplicands,

wherein the complex multiplication is used in one of scrambling and descrambling spread spectrum communications signals.

2. The method of claim 1 wherein the phasor constant has a value selected so that for each possible value of the complex multiplicand, the complex product has an imaginary value equal to one of the real value of the complex multiplicand, the imaginary value of the complex multiplicand, the negation of the real value of the complex multiplicand, and the negation of the imaginary value of the complex multiplicand for each possible value of the complex multiplicand.

3. The method of claim 1 wherein the multiplicand is a complex chip value for generating a spread spectrum communications signal.

4. The method of claim 1 wherein the multiplier is a complex scrambling code for transmitting a spread spectrum communications signal.

5. The method of claim 1 wherein the multiplier is a complex descrambling code for receiving a spread spectrum communications signal.

6. The method of claim 1 wherein the phasor constant has a phase angle of one of 45, 135, 225, and 315 degrees.

7. The method of claim 1 wherein the phasor constant results in an overall gain of unity in the complex product.

8. The method of claim 1 further comprising a step of generating as output a real value of the complex product by selecting one of the real value of the complex multiplicand, the imaginary value of the complex multiplicand, the negation of the real value of the complex multiplicand, and the negation of the imaginary value of the complex multiplicand.

9. The method of claim 1 further comprising a step of generating as output an imaginary value of the complex product by selecting one of the real value of the complex multiplicand, the imaginary value of the complex multiplicand, the negation of the real value of the complex multiplicand, and the negation of the imaginary value of the complex multiplicand.

10. An apparatus for complex multiplication comprising:

a first negation block for receiving a real value of a complex multiplicand and for generating a negation of the real value of the complex multiplicand;

a second negation block for receiving an imaginary value of the complex multiplicand and for generating a negation of the imaginary value of the complex multiplicand; and

a selector coupled to the first negation block and the second negation block for generating a complex product of the complex multiplicand times a complex multiplier times a phasor constant wherein the phasor constant has a value selected so that for each possible value of the complex multiplicand, the complex product has a real value equal to one of the real value of the complex multiplicand, the imaginary value of the complex multiplicand, the negation of the real value of the complex multiplicand, and the negation of the imaginary value of the complex multiplicand.

11. The apparatus of claim 10 wherein the phasor constant has a value selected so that for each value of the complex multiplicand, the complex product has an imaginary value equal to one of the real value of the complex multiplicand, the imaginary value of the complex multiplicand, the negation of the real value of the complex multiplicand, and the negation of the imaginary value of the complex multiplicand for each possible value of the complex multiplicand.

12. The apparatus of claim 10 wherein the multiplicand is a complex chip value for generating a spread spectrum communications signal.

13. The apparatus of claim 10 wherein the multiplier is a complex scrambling code for transmitting a spread spectrum communications signal.

14. The apparatus of claim 10 wherein the multiplier is a complex descrambling code for receiving a spread spectrum communications signal.

15. The apparatus of claim 10 wherein the phasor constant has a phase angle of one of 45, 135, 225, and 315 degrees.

16. The apparatus of claim 10 wherein the phasor constant results in an overall gain of unity in the complex product.

17. The apparatus of claim 10 wherein the complex product is representative of a scrambled chip of a spread spectrum communications signal.

18. The apparatus of claim 10 wherein the complex product is representative of a descrambled chip of a spread spectrum communications signal.

19. The apparatus of claim 10 wherein the complex product is representative of a scrambled chip of a spread spectrum communications signal transmitted from a cellular telephone.

20. The apparatus of claim 10 wherein the complex product is representative of a descrambled chip of a spread spectrum communications signal received by a cellular telephone.