IP Library Granted Patent US 7,324,560
Granted Patent B2
US 7,324,560 · App. 10/603,123 · Granted Jan 29, 2008

Recovering clock and frame information from data stream

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Quick Facts
Patent No.
US 7,324,560
App. No.
10/603,123
Granted
Jan 29, 2008
Kind
B2
Abstract

A method for transmitting a digital data stream includes recovery of data clock information and data frame information from the digital data stream. The method includes providing a digital data stream having successive data stream units. Each data stream unit includes a data frame, a data block having data bits, and a frame synchronization word having frame synchronization bits. Successive frame synchronization words of the successive data stream units are then detected and data clock information is determined from a temporal spacing of the successive frame synchronization words. The data clock information is then output in a manner dependent on a temporal spacing of successive frame synchronization bits.

Claims (33)

1. A method for transmitting a digital data stream, in which method data clock information and data frame information are recovered from the digital data stream, the method comprising:

providing a digital data stream having successive data stream units, each data stream unit including

a data frame,

a data block having data bits, and

a frame synchronization word having frame synchronization bits; wherein a frame start of a data frame is defined when a plurality of dummy bits precedes a frame synchronization word, the plurality being at least one greater than the sum of the number of frame synchronization bits in the frame synchronization word and the number of data bits in the data block;

receiving the digital data stream;

detecting successive frame synchronization words of the successive data stream units;

determining the data clock information from a temporal spacing of the successive frame synchronization words; and

outputting the data clock information in a manner dependent on a temporal spacing of successive frame synchronization bits.

2. The method of claim 1 , wherein providing a digital data stream comprises preceding the data bits of the data block by two frame synchronization bits.

3. The method of claim 1 , wherein providing a digital data stream comprises encompassing useful data to be transmitted with the data bits of each data block.

4. The method of claim 1 , wherein providing a digital data stream comprises providing a 32-bit data block.

5. The method of claim 1 , further comprising selecting the dummy bits to be logic ones.

6. The method of claim 1 , wherein providing a digital data stream comprises including header data in a first data block of each data frame.

7. The method of claim 6 , further comprising including superframe synchronization bits in the header data.

8. The method of claim 7 , further comprising including information indicative of the start of an assigned superframe in the superframe synchronization bits, the start being indicated by logic zeroes.

9. A data stream receiver for receiving and processing a digital data stream, the data stream receiver comprising:

a data stream reception unit for receiving a digital data stream having at least one data stream unit that includes a frame synchronization word having frame synchronization bits and a data block having data bits;

a synchronization bit detection unit for detecting the frame synchronization wordsof successive data blocks of the digital data stream;

a data clock determination unit for determining a data clock from a temporal spacing of successive frame synchronization words from the digital data stream; and

a frame detection unit for detecting a frame start, wherein the frame start of a data frame is defined when a plurality of dummy bits precedes a frame synchronization word, the plurality being at least one greater than the sum of the number of frame synchronization bits in the frame synchronization word and the number of data bits in the data block.

10. The data stream receiver of claim 9 , further comprising a superframe detection unit for detecting a superframe start.

11. A manufacture having encoded thereon a digital data stream transmitted by a method for transmitting a digital data stream, in which method data clock information and data frame information are recovered from the digital data stream, the method comprising:

providing a digital data stream having successive data stream units, each data stream unit including a data frame, a data block having data bits, and a frame synchronization word having frame synchronization bits; wherein a frame start of a data frame is defined when a plurality of dummy bits precedes a frame synchronization word, the plurality being at least one greater than the sum of the number of frame synchronization bits in the frame synchronization word and the number of data bits in the data block;

receiving the digital data stream;

detecting successive frame synchronization words of the successive data stream units;

determining the data clock information from a temporal spacing of the successive frame synchronization words; and

outputting the data clock information in a manner dependent on a temporal spacing of successive frame synchronization bits.

12. An interface module that includes a data stream receiver for receiving and processing a digital data stream, the data stream receiver comprising:

a data stream reception unit for receiving a digital data stream having at least one data stream unit that includes a frame synchronization word having frame synchronization bits and a data block having data bits;

a synchronization bit detection unit for detecting the frame synchronization words of successive data blocks of the digital data stream; and

a data clock determination unit for determining a data clock from a temporal spacing of successive frame synchronization words from the digital data stream; and

a frame detection unit for detecting a frame start, wherein the frame start of a data frame is defined when a plurality of dummy bits precedes a frame synchronization word, the plurality being at least one greater than the sum of the number of frame synchronization bits in the frame synchronization word and the number of data bits in the data block.

Assignments (9)
SECURITY AGREEMENT Recorded Jul 9, 2021
From: MAXLINEAR, INC.; MAXLINEAR COMMUNICATIONS, LLC; EXAR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 056816/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2020
From: INTEL CORPORATION
To: MAXLINEAR, INC.
Reel/Frame 053626/0636 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2020
From: LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: INTEL CORPORATION
Reel/Frame 053259/0678 →
MERGER AND CHANGE OF NAME Recorded Jan 17, 2018
From: LANTIQ DEUTSCHLAND GMBH; LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 045086/0015 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 025413/0340 AND 025406/0677 Recorded Apr 17, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 035453/0712 →
GRANT OF SECURITY INTEREST IN U.S. PATENTS Recorded Nov 29, 2010
From: LANTIQ DEUTSCHLAND GMBH
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 025406/0677 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
To: LANTIQ DEUTSCHLAND GMBH
Reel/Frame 024529/0635 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2010
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
Reel/Frame 024474/0958 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2003
From: MUELLER, REINHARD
To: INFINEON TECHNOLOGIES AG
Reel/Frame 014658/0617 →