IP Library Granted Patent US 6,967,538
Granted Patent B2
US 6,967,538 · App. 10/603,647 · Granted Nov 22, 2005

PLL having VCO for dividing frequency

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,967,538
App. No.
10/603,647
Granted
Nov 22, 2005
Kind
B2
Abstract

A PLL comprising a phase detector, a loop filter and a VCO is disclosed. The phase detector periodically compares an externally inputted clock signal with a frequency of an internal clock signal, and outputs an output signal resulting from phase difference of the two signals. The loop filter outputs a predetermined voltage in response to an output signal from said phase detector. The VCO outputs said internal clock signal having a frequency proportional to said predetermined voltage. Here, the VCO includes a capsule for adjusting the value of capacitance using an internal control signal. As a result, frequencies may be pre-compensated by control signals used in the PLL. In addition, the disclosed PLL having a VCO therein can be configured into a single chip, thereby simplifying the embodiment of the whole PLL and enabling accurate compensation.

Claims (10)

1. A PLL comprising:

a phase detector for periodically comparing an externally inputted clock signal with a frequency of an internal clock signal, and outputting an output signal resulting from phase difference between the two signals;

a loop filter for outputting a predetermined voltage in response to an output signal from said phase detector; and

a VCO for outputting said internal clock signal having a frequency proportional to said predetermined voltage,

wherein said VCO comprises a capsule for adjusting the value of capacitance by using an internal control signal, said capsule comprising:

a plurality of first capacitors connected in parallel to an output terminal of said VCC.

2. The PLL according to claim 1 , wherein said capsule comprises a plurality of first switches connected, between said output terminal and the plurality of said first capacitors, respectively, and to be controlled in response to a plurality of control signals generated by using said internal control signal.

3. The PLL according to claim 1 , wherein said capsule comprises a plurality of second capacitors connected in series between output terminals of said VCO.

4. The PLL according to claim 3 , wherein said capsule comprises a plurality of second switches configured to be connected between an output terminal and the plurality of said second capacitors, and to be controlled in response to a plurality of control signals generated by using said internal control signal.

5. The PLL according to claim 4 , wherein the plurality of said second switches is connected in parallel between an output terminal and the plurality of said second capacitors.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2006
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: ABOV SEMICONDUCTOR CO., LTD.
Reel/Frame 017379/0378 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2003
From: WOO, SUNG HUN
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 014533/0091 →