METHOD OF FABRICATING LOW TEMPERATURE POLYSILICON THIN FILM TRANSISTOR
First, a substrate with a polysilicon film is provided. Then, a gate insulating layer and a gate are formed on the polysilicon film in sequence. An ion implantation process is performed to form a source and a drain around the gate. After that, a first plasma enhanced chemical vapor deposition (PECVD) process is performed to form a silicon nitride layer over the substrate and the gate. A second plasma enhanced chemical vapor deposition process is then performed to form a TEOS based silicon oxide layer on the silicon nitride layer. A photo-etching process follows to form a contact hole extending through to the source and drain respectively. Then, a conductive layer is filled into the contact holes and electrically connected to the source and drain.
1 : A method of fabricating a thin film transistor (TFT) comprising:
providing a substrate;
forming a polysilicon film on the substrate, the polysilicon film defined with a source region, a drain region, and a channel region between the source region and the drain region;
forming a gate insulating layer above the substrate;
forming a gate above the substrate;
performing an ion implantation process to form a source in the source region and a drain in the drain region;
forming a silane based silicon nitride layer covering the gate and the polysilicon film; and
forming a TEOS based silicon oxide layer on the silicon nitride layer.
2 : The method of claim 1 further comprising following steps:
performing a photo-etching process to form a contact hole on the source and drain respectively; and
filling a conductive layer in the contact holes, the conductive layer being electrically connected to the source and the drain.
3 : The method of claim 1 wherein the method of forming the polysilicon film comprises following steps:
forming an amorphous silicon film on the substrate; and
performing an excimer laser annealing process to make the amorphous silicon film crystallize to the polysilicon film.
4 (cancelled)
5 : The method of claim 4 wherein the silicon nitride layer comprises 20% to 40% hydrogen atoms and serves as a hydrogen source of a hydrogenating process.
6 : The method of claim 1 wherein the gate is a metal gate.
7 : The method of claim 1 wherein the silicon oxide has a thickness in a range of 500 to 10000 angstroms.
8 : The method of claim 1 wherein the silicon nitride has a thickness in a range of 500 to 5000 angstroms.
9 : The method of claim 1 wherein the method forms the silicon nitride layer by performing a first plasma enhanced chemical vapor deposition (PECVD) process.
10 : The method of claim 9 wherein the method forms the silicon oxide layer by performing a second plasma enhanced chemical vapor deposition process.
11 : The method of claim 10 wherein the first PECVD process and the second PECVD process are performed in the same reacting chamber.
12 : The method of claim 10 wherein the first PECVD process and the second PECVD process are performed in different chambers.
13 : The method of claim 1 wherein the low temperature polysilicon thin film transistor is a top gate low temperature polysilicon thin film transistor or a bottom gate low temperature polysilicon thin film transistor.