IP Library Granted Patent US 6,891,210
Granted Patent B2
US 6,891,210 · App. 10/606,836 · Granted May 10, 2005

Semiconductor device having a protection circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,891,210
App. No.
10/606,836
Granted
May 10, 2005
Kind
B2
Abstract

The semiconductor device includes a plurality of transistors, wherein one of the transistors that has the thinnest gate dielectric layer is selected to serve as a power source protection element, among a plurality of transistors, each having a gate dielectric layer of an independently set film thickness, disposed on a same substrate to be operated by a voltage from a same power source. Also, a threshold voltage of the transistor selected as the power source protection element is set higher than other transistor that also has the thinnest gate dielectric layer.

Claims (13)

1. A semiconductor device comprising:

a substrate; and

a plurality of groups of transistors formed on said substrate to be operated by a common voltage generated by a power source, each group of said plurality of groups of transistors having a gate dielectric layer differing in thickness from that of the other groups of said plurality of groups of transistors,

wherein one group in said plurality of groups of transistors having a thinnest gate dielectric layer; one transistor in said one group is selected to serve as a power source protection element,

wherein said one transistor selected as the power source protection element has a higher threshold voltage than the other transistors in said one group, and

wherein said one transistor selected as the power source protection element has a diode type connection.

2. The semiconductor device as set forth in claim 1 , wherein said plurality of groups of transistors include at least three types of transistors each having different combinations of thickness of the gate dielectric layer and threshold voltage from each other.

3. The semiconductor device as set forth in claim 1 , wherein said plurality of groups of transistors are disposed in an internal circuit surrounded by an I/O interface region.

4. The semiconductor device as set forth in claim 1 , wherein said plurality of groups of transistors include a high speed processing type transistor and a low power consumption type transistor, and said transistor selected to serve as the power source protection element has a higher threshold voltage than that of said high speed processing type transistor.

5. The semiconductor device as set forth in claim 1 , wherein said plurality of groups of transistors include a high speed processing type transistor and a low power consumption type transistor, and said transistor selected to serve as the power source protection element has a gate dielectric layer thickness which is the same as or thinner than that of said high speed processing type transistor.

6. The semiconductor device as set forth in claim 1 , wherein said plurality of groups of transistors include a high speed processing type transistor and a low power consumption type transistor, and leak current of said transistor selected to serve as the power source protection element is smaller than that of said high speed processing type transistor.

7. The semiconductor device as set forth in claim 1 , wherein said plurality of groups of transistors include a high speed processing type transistor and a low power consumption type transistor, and said transistor selected to serve as the power source protection element has a higher threshold voltage than that of said high speed processing type transistor, and said transistor selected to serve as the power source protection element has a gate dielectric layer thickness which is the same as or thinner than that of said high speed processing type transistor.

8. The semiconductor device as set forth in claim 7 , wherein said plurality of groups of transistors are disposed in an internal circuit surrounded by an I/O interface region.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Dec 22, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025525/0145 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2003
From: AKIYAMA, NAOTO
To: NEC ELECTRONICS CORPORATION
Reel/Frame 014239/0665 →