Maintaining cache integrity by recording write addresses in a log
An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver. In an embodiment, a non-volatile cache may be implemented by creating a device option read only memory (ROM), or modifying the associated computer basic input-output system (BIOS) to trap software interrupts associated with disk and other media access requests. Associated addresses, such as logical block addresses, can be stored in a log for data that is modified. The resulting log can be stored in a non-volatile medium, including the cache itself. If the available log space is not large enough to record all write activity prior to loading operating system drivers, a flag may be set to indicate the overrun condition.
1. A method, comprising:
recording an address of a write operation to a memory having information cached by a non-volatile cache prior to executing an operating system cache driver associated with the non-volatile cache;
recording the address of the write operation in a log;
setting a flag to indicate an overrun of the log; and
invalidating the information if the flag is set.
2. The method of claim 1 , wherein the log is stored in a memory comprising at least one of a static random access memory (SRAM), a dynamic random access memory (DRAM), a flash memory, and a polymer ferroelectric RAM (PFRAM).
3. The method of claim 1 , further comprising:
detecting the write operation.
4. The method of claim 3 , wherein detecting the write operation further comprises:
trapping an interrupt request.
5. The method of claim 1 , further comprising:
modifying data corresponding to the address of the write operation.
6. The method of claim 5 , wherein modifying the data corresponding to the address of the write operation further comprises:
updating the data corresponding to the address of the write operation.
7. The method of claim 5 , wherein modifying the data corresponding to the address of the write operation further comprises:
invalidating the data corresponding to the address of the write operation.
8. An article comprising a machine-accessible medium having associated data, wherein the data, when accessed, results in a machine performing:
recording an address of a write operation to a memory having information cached by a non-volatile cache prior to executing an operating system cache driver associated with the non-volatile cache;
recording the address of the write operation in a log;
setting a flag to indicate an overrun of the log; and
invalidating the information if the flag is set.
9. The article of claim 8 , wherein the log is included in a non-volatile memory.
10. An apparatus, comprising:
a non-volatile cache;
a first memory to store an address associated with a write operation to a second memory having information cached by the non-volatile cache prior to executing an operating system cache driver associated with the non-volatile cache;
the first memory to record the address of the write operation in a log; and
a machine to set a flag to indicate an overrun of the log; and
the machine to invalidate the information if the flag is set.
11. The apparatus of claim 10 , wherein the address is a logical block address.
12. The apparatus of claim 10 , wherein the first memory to store an address comprises a non-volatile memory.
13. The apparatus of claim 10 , further comprising:
a module to receive an interrupt request associated with the write operation.
14. The apparatus of claim 13 , wherein the interrupt request is a basic input-output system Int13h request.
15. A system, comprising:
a non-volatile cache;
a first memory to store an address associated with a write operation to a second memory having information cached by the non-volatile cache prior to executing an operating system cache driver associated with the non-volatile cache;
a processor coupled to the first memory to store an address;
the first memory to record the address of the write operation in a log;
the processor to set a flag to indicate an overrun of the log;
the processor to invalidate the information if the flag is set; and
a display coupled to the processor.
16. The system of claim 15 , further comprising:
a module to receive an interrupt request associated with the write operation.
17. The system of claim 16 , wherein the module is included in a device option memory.
18. The system of claim 16 , wherein the module is included in a basic input-output system.
19. The system of claim 15 , wherein the first memory to store an address comprises a non-volatile memory to store the log including a plurality of memory addresses including the address of the write operation.