Dynamic multiple cluster system reconfiguration
View Patent ↗According to the present invention, methods and apparatus are provided to allow dynamic multiple cluster system configuration changes. In one example, processors in the multiple cluster system share a virtual address space. Mechanisms for dynamically introducing and removing processors, I/O resources, and clusters are provided. The mechanisms can be implemented during reset or while a system is operating. Links can be dynamically enabled or disabled.
1. A method comprising:
terminating a plurality of applications running in an operating system environment that supports dynamic removal of a first processor cluster from a plurality of processor clusters, the first processor cluster including a first plurality of processors and a first interconnection controller interconnected using a point-to-point architecture;
identifying the first processor cluster for removal;
flushing a plurality of caches associated with the first processor cluster;
modifying a plurality of routing tables associated with each processor cluster to reflect removal of the first processor cluster;
disabling link layer communications associated with the first processor cluster, wherein the first processor cluster is disconnected after disabling link layer communications associated with the first processor cluster;
maintaining physical layer communications associated with the first processor cluster to allow connection of a replacement processor cluster.
2. The method of claim 1 , wherein a fence bit is written by a service processor.
3. The method of claim 1 , wherein a fence bit is written by a JTAG interface associated with a processor.
4. The method of claim 1 , wherein the first cluster of processors and a second cluster of processors share a single virtual address space.
5. The method of claim 4 , wherein the second cluster of processors includes a second interconnection controller.
6. The method of claim 5 , wherein the second interconnection controller includes a physical layer enable indicator.
7. The method of claim 5 , wherein the second interconnection controller includes a fence indicator configurable to prevent the transmission of logical packets between the first interconnection controller and the second interconnection controller.
8. The method of claim 5 , wherein the second interconnection controller includes a reinitialization indicator configurable to direct the second interconnection controller to reinitialize the link.
9. An apparatus comprising:
means for terminating a plurality of applications running in an operating system environment that supports dynamic removal of a first processor cluster from a plurality of processor clusters, the first processor cluster including a first plurality of processors and a first interconnection controller interconnected using a point-to-point architecture;
means for identifying a first processor cluster for removal;
means for flushing a plurality of caches associated with the first processor cluster;
means for modifying a plurality of routing tables associated with each processor cluster to reflect removal of the first processor cluster;
means for disabling link layer communications associated with the first processor cluster, wherein the first processor cluster is disconnected after disabling link layer communications associated with the first processor cluster;
means for maintaining physical layer communications associated with the first processor cluster to allow connection of a replacement processor cluster.
10. The apparatus of claim 9 , wherein a fence bit is written by a service processor.
11. The apparatus of claim 9 , wherein a fence bit is written by a JTAG interface associated with a processor.
12. The apparatus of claim 9 , wherein the first cluster of processors and the second cluster of processors share a single virtual address space.