IP Library Granted Patent US 7,256,486
Granted Patent B2
US 7,256,486 · App. 10/608,605 · Granted Aug 14, 2007

Packaging device for semiconductor die, semiconductor device incorporating same and method of making same

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Quick Facts
Patent No.
US 7,256,486
App. No.
10/608,605
Granted
Aug 14, 2007
Kind
B2
Abstract

The packaging device includes a substrate, a mounting pad, a connecting pad and an interconnecting element. The substrate is substantially planar and has opposed major surfaces. The mounting pad is conductive and is located on one of the major surfaces. The connecting pad is conductive and is located on the other of the major surfaces. The conductive interconnecting element extends through the substrate and electrically interconnects the mounting pad and the connecting pad. The packaging device has a volume that is only a few times that of the semiconductor die and can be fabricated from materials that can withstand high-temperature die attach processes. The packaging device can be configured as the only packaging device used in the semiconductor device or as a submount for a semiconductor die that requires a high-temperature die attach process.

Claims (15)

1. A semiconductor device, comprising:

a substantially planar substrate having opposed major surfaces;

an electrically conductive mounting pad located on one of the major surfaces of the substrate;

a light emitting diode (LED) having a metallized bottom major surface that is mounted on the electrically conductive mounting pad, the metallized bottom major surface comprising one of an anode and a cathode of the LED;

a first electrically conductive connecting pad located on the other of the major surfaces of the substrate; and

a first electrically conductive interconnecting element extending through the substrate and electrically interconnecting the mounting pad and the first electrically conductive connecting pad.

2. The semiconductor device of claim 1 , further comprising:

an electrically conductive bonding pad located on the one of the major surfaces of the substrate;

a bonding wire extending between a metallized top major surface of the LED and the electrically conductive bonding pad;

a second electrically conductive connecting pad located on the other of the major surfaces of the substrate; and

a second electrically conductive interconnecting element extending through the substrate and electrically interconnecting the bonding pad and the second connecting pad.

3. The semiconductor device of claim 2 wherein the metallized top major surface comprises a first electrode of the LED and the metallized bottom major surface comprises a second electrode of the LED.

4. The semiconductor device of claim 1 wherein the first electrically conductive interconnecting element is selected to withstand an operating temperature when the LED is mounted on the electrically conductive mounting pad and to provide a low-resistance electrical connection between the mounting pad and the first electrically conductive connecting pad.

5. The semiconductor device of claim 4 , wherein the first electrically conductive interconnecting element comprises tungsten.

6. The semiconductor device of claim 4 , wherein the first electrically conductive interconnecting element comprises a slug of electrically conductive material, the slug having a diameter selected to press-fit the slug into a through hole located in the substrate between the mounting pad and the first electrically conductive connecting pad.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2016
From: INTELLECTUAL DISCOVERY CO. LTD.
To: DOCUMENT SECURITY SYSTEMS, INC.
Reel/Frame 040744/0174 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2012
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.; AVAGO TECHNOLOGIES FIBER IP (SINGAPORE) PTE. LTD.
To: INTELLECTUAL DISCOVERY CO., LTD.
Reel/Frame 028972/0733 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0518 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2003
From: LEE, KONG WENG; NG, KEE YEAN; KUAN, YEW CHEONG; TAN, GIN GHEE; TAN, CHENG WHY
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 014013/0943 →