IP Library Granted Patent US 6,921,949
Granted Patent B2
US 6,921,949 · App. 10/609,957 · Granted Jul 26, 2005

Semiconductor integrated circuit device

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Quick Facts
Patent No.
US 6,921,949
App. No.
10/609,957
Granted
Jul 26, 2005
Kind
B2
Abstract

A semiconductor integrated circuit device is comprised of an amplifier circuit having first and second PMOS and NMOS transistors. The first PMOS transistor has a gate electrode and a drain electrode connected together. The second PMOS transistor has a gate electrode connected to the gate electrode of the first PMOS transistor and a course electrode connected to a course electrode of the first PMOS transistor. The first NMOS transistor has a drain electrode connected to the drain electrode of the first PMOS transistor and a gate electrode sat as a first input terminal. The second NMOS transistor has a drain electrode connected to a drain electrode of the second PMOS transistor, a source electrode connected to a sourse electrode of the first NMOS transistor, and a gate electrode sat as a second input terminal. At least one of the first NMOS transistor and the second NMOS transistor is comprised of a buried channel transistor.

Claims (7)

1. A semiconductor integrated circuit device comprising: an amplifier circuit comprised of a first PMOS transistors having a gate electrode and a drain electrode connected together, a second PMOS transistor having a gate electrode connected to the gate electrode of the first PMOS transistor and a source electrode connected to a source electrode of the first PMOS transistor, a first NMOS transistor having a drain electrode connected to the drain electrode of the first PMOS transistor and a gate electrode set as a first input terminal, and second NMOS transistor having a drain electrode connected to a drain electrode of the second PMOS transistor, a source electrode connected to a source electrode of the first NMOS transistor, and a gate electrode set as a second input terminal, at least one of the first NMOS transistor and the second NMOS transistor being comprised of a buried channel transistor; wherein the semiconductor integrated circuit device comprises an A/D converter.

2. A semiconductor integrated circuit device comprising: an amplifier circuit comprised of a first PMOS transistor having a gate electrode and a drain electrode connected together, a second PMOS transistor having a gate electrode connected to the gate electrode of the first PMOS transistor and a sourse electrode connected to a sourse electrode of the first PMOS transistor,a first NMOS transistor having a drain electrode connected to the drain electrode of the first PMOS transistor and a gate electrode set a first input terminal, and a second NMOS transistor having a drain electrode connected to a drain electrode of the second PMOS transistor, a sourse electrode connected to a sourse electrode of the first NMOS transistor, and a gate electrode set as a second terminal, at least one of the first NMOS transistor and the second NMOS transistor being comprised of a buried channel transistor; wherein the semiconductor integrated circuit device comprises an D/A converter.

3. A semiconductor integrated circuit device comprising: an amplifier circuit comprised of a first surface channel PMOS transistor having a gate electrode and a drain electrode connected together, a second surface channel PMOS transistor having a gate electrode connected to the gate electrode of the first surface channel PMOS transistor and a source electrode connected to a sourse electrode of the first surface channel PMOS transistor, a first buried channel NMOS transistor having a drain electrode connected to the drain electrode of the first surface channel PMOS transistor and a gate electrode set as a first input terminal, and a second buried channel NMOS transistor having a drain electrode connected to a drain electrode of the second surface channel PMOS transistor, a sourse electrode connected to a sourse electrode of the first buried channel NMOS transistor, and a gate electrode set as a second input terminal; wherein the semiconductor integrated circuit device comprises a A/D converter.

4. A semiconductor integrated circuit device according to claim 3 ; wherein the gate electrode of at least one of the first buried channel NMOS transistor and second buried channel NMOS transistor is formed of P-type polycrystalline silicon.

5 .A semiconductor integrated circuit device according to claim 3 ; wherein the gate electrode of each of the first buried channel NMOS transistor and the second buried channel NMOS transistor is formed of P-type polycrystalline silicon.

6. A semiconductor integrated circuit device comprising: an amplifier circuit comprised of a first surface channel PMOS transistor having a gate electrode and a drain electrode connected together, a second surface channel PMOS transistor having a gate electrode connected to the gate electrode of the first surface channel PMOS transistor and a source electrode connected to a sourse electrode of the first surface channel PMOS transistor, a first buried channel NMOS transistor having a drain electrode connected to the drain electrode of the first surface channel PMOS transistor and a gate electrode set as a first input terminal, and a second buried channel NMOS transistor having a drain electrode connected to a drain electrode of the second surface channel PMOS transistor, a source electrode connected to a source electrode of the first buried channel NMOS transistor, and a gate electrode sat as a second input terminal, wherein the semiconductor integrated circuit device comprises a D/A converter.

7. A semiconductor integrated circuit device according to claim 3 ; wherein the gate electrode of each of the first buried channel NMOS transistor and the second buried channel NMOS transistor comprises a P-type gate electrode.

Assignments (3)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2016
From: SEIKO INSTRUMENTS INC.
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 038058/0892 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2005
From: HARADA, HIROFUMI; OSANAI, JUN
To: SEIKO INSTRUMENTS INC.
Reel/Frame 016709/0836 →