IP Library Granted Patent US 7,342,300
Granted Patent B2
US 7,342,300 · App. 10/610,497 · Granted Mar 11, 2008

Integrated circuit incorporating wire bond inductance

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Quick Facts
Patent No.
US 7,342,300
App. No.
10/610,497
Granted
Mar 11, 2008
Kind
B2
Abstract

The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack, a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond inductance and uses it in an operational circuit where positive inductance is required. The circuit in which the wire bond inductance is used is located primarily in the integrated circuit die housed in the integrated circuit package, but may also include off-die components. In one example, a wire bond is used as the required series inductance in a discrete circuit impedance inverter which consists of two shunt-to-ground negative inductances and one series positive inductance. One of the negative inductances is located on-die, while the other is located off-die.

Claims (33)

1. An integrated circuit package comprising:

an integrated circuit die having at least one integrated circuit and a first negative-inductance shunt element

a housing containing said integrated circuit die, wherein said integrated circuit die is electrically coupled to said housing using at least one wire bond; and

an impedance inverter circuit including the first negative-inductance shunt element, the at least one wire bond, and a second negative-inductance shunt element coupled to the integrated circuit die through the at least one wire bond.

2. The integrated circuit of claim 1 , wherein at least one of the first negative-inductance shunt element and the second negative-inductance shunt element has a negative inductance only over a limited bandwidth.

3. The integrated circuit of claim 2 , wherein at least one of the first negative-inductance shunt element and the second negative-inductance shunt element having the negative inductance only over the limited bandwidth includes a capacitor configured to have the negative inductance only over the limited bandwidth.

4. The integrated circuit of claim 1 , wherein the second negative-inductance shunt element is external to the housing.

5. An integrated circuit package comprising:

an integrated circuit die having at least one integrated circuit, the integrated circuit comprising elements that require theoretically negative reactive component values;

a housing containing said integrated circuit die, wherein said integrated circuit die is electrically coupled to said housing using at least one wire bond; and where the at least one wire bond has an inductance associated therewith, and comprises a series inductor of a series inverter portion of an impedance inverter circuit; and wherein the negative reactive component values theoretically required by the integrated circuit are incorporated into the integrated circuit through the use of the impedance inverter circuit;

a first inductor electrically coupled to the series inverter portion at a first node, wherein the first inductor is arranged in a shunt arrangement; and

a second inductor electrically coupled to the series inverter portion at a second node, wherein the second inductor is arranged in a shunt arrangement.

6. The integrated circuit package of claim 5 , wherein at least one of the said first and second inductors are formed external to said integrated circuit die.

7. The integrated circuit package of claim 5 , wherein one of said first and second inductors is formed external to said integrated circuit die and the other of said first and second inductors is formed integrally with said integrated circuit die.

8. The integrated circuit package of claim 5 , wherein each of said first and second inductors is formed integrally with said integrated circuit die.

9. The integrated circuit package of claim 5 , wherein each of said first and second inductors include a spiral inductor.

10. The integrated circuit package of claim 5 , wherein said series inductor, said first and said second inductors are part of the impedance inverter, the impedance inverter adapted to transform a lower output impedance into a higher output impedance.

11. The integrated circuit package of claim 5 , wherein at least one of said first and second inductors has a negative inductance.

12. The integrated circuit package of claim 5 , wherein at least one of said first and second inductors are formed external to the housing.

13. An integrated circuit package comprising:

an integrated circuit die having at least one integrated circuit, the integrated circuit comprising elements that require theoretically negative reactive component values;

a housing containing said integrated circuit die, wherein said integrated circuit die is electrically coupled to said housing using at least one wire bond; and where the at least one wire bond has an inductance associated therewith; and

means for incorporating the negative reactive component values into the integrated circuit, the means for incorporating the negative reactive component values including:

a series inverter portion including the at least one wire bond as a series inductor;

a first inductor electrically coupled to the series inverter portion at a first node, wherein the first inductor is arranged in a shunt arrangement; and

a second inductor electrically coupled to the series inverter portion at a second node, wherein the second inductor is arranged in a shunt arrangement.

14. The integrated circuit package of claim 13 , wherein at least one of said first and second inductors are formed external to said integrated circuit die.

15. The integrated circuit package of claim 13 , wherein one of said first and second inductors is formed external to said integrated circuit die and the other of said first and second inductors is formed integrally with said integrated circuit die.

16. The integrated circuit package of claim 13 , wherein each of said first and second inductors is formed integrally with said integrated circuit die.

17. The integrated circuit package of claim 13 , wherein each of said first and second inductors include a spiral inductor.

18. The integrated circuit package of claim 13 , wherein the means for incorporating the negative reactive component values into the integrated circuit is adapted to transform a lower output impedance into a higher output impedance.

19. The integrated circuit package of claim 13 , wherein at least one of said first and second inductors has a negative inductance.

20. The integrated circuit package of claim 13 , wherein at least one of said first and second inductors are formed external to the housing.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2005
From: ICEFYRE SEMICONDUCTOR, INC.
To: ZARBANA DIGITAL FUND, LLC
Reel/Frame 017388/0432 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2005
From: ICEFYRE SEMICONDUCTOR CORPORATION
To: ICEFYRE SEMICONDUCTOR, INC.
Reel/Frame 017262/0905 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2003
From: J.S. WIGHT, INC.
To: ICEFYRE SEMICONDUCTOR CORPORATION
Reel/Frame 014282/0806 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2003
From: GRUNDLINGH, JOHAN M.
To: ICEFYRE SEMICONDUCTOR CORPORATION
Reel/Frame 014282/0817 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2003
From: WIGHT, JAMES STUART
To: J.S. WIGHT INC.
Reel/Frame 014282/0883 →