Pseudo-noise code hopping method and apparatus
View Patent ↗A PN code hopping method for mitigating cross-correlation interference is provided. The method includes the steps of providing a memory device and storing a plurality of PN codes, where each PN code is associated with a useful life cycle. The PN codes are pseudo-randomly accessed and used to spread a modulated signal for their respective useful life cycle before another PN code is pseudo-randomly retrieved.
1. A PN code hopping device comprising:
at least one memory device, wherein the at least one memory device comprises:
a plurality of time limited PN codes;
an addressable multiplexer, wherein the addressable multiplexer is coupled to the at least one memory device;
an address generator wherein the address generator is coupled to the addressable multiplexer;
a N-x-Spreading Factor (SF) storage capacity, where N is an integer equal to a number of chips and SF is equal to N/symbol;
a universal serial bus (USB) port; and
a serial to N-parallel converter.
2. A PN code hopping device as in claim 1 wherein the at least one memory device further comprises:
a N-x-Spreading Factor (SF) storage capacity, where N is an integer equal to a number of chips and SF is equal to N/symbol; and
N-parallel outputs.
3. A PN code hopping device as in claim 1 wherein the addressable multiplexer comprises a N:1 multiplexer where N is an integer equal to a number of chips associated with one of the plurality of time limited PN codes.
4. A PN code hopping device as in claim 1 wherein the address generator comprises a look-up-table (LUT).
5. A PN code hopping device as in claim 1 wherein the address generator comprises a shift register.
6. A PN code hopping device as in claim 1 wherein the address generator comprises:
an up-down counter; and
a look-up-table, wherein the look-up-table is coupled to the up-down counter.
7. A pseudo noise (PN) code hopping system for mitigating cross-correlation interference between Direct Sequence-Code Division Multiple Access (DS-CDMA) users, the system comprising:
a first PN code hopping module, wherein the first PN code hopping module comprises:
a first memory device;
a first addressable multiplexer, wherein the addressable multiplexer is coupled to the first memory device;
a first address generator, wherein the first address generator is coupled to the first addressable multiplexer;
a second PN code hopping module, the second PN code hopping module is coupled to the first PN code hopping module, wherein the second PN code hopping module comprises:
a second memory device;
a second addressable multiplexer, wherein the addressable multiplexer is coupled to the second memory device; and
a second address generator, wherein the second address generator is coupled to the second addressable multiplexer.
8. A PN code hopping system as in claim 7 wherein the first memory device comprises:
a first modulation matrix of size L×L, where L is an integer equal to SF max /SF min , and where SF max is a maximum spread factor and SF min is a minimum spread factor and where SF max and SF min are integers, wherein the first modulation matrix comprises a first set of time limited PN codes; and
L parallel outputs.
9. A PN code hopping system as in claim 7 wherein the first addressable multiplexer comprises a L:1 multiplexer.
10. A PN code hopping system as in claim 7 wherein the first address generator comprises:
a first up-down counter; and
a first look-up-table (LUT), the first LUT coupled to the first up-down counter.
11. A PN code hopping system as in claim 7 wherein the first address generator comprises a first shift register.
12. A PN code hopping system as in claim 7 wherein the second memory device comprises:
a second modulation matrix of size P×nP, where P=SF max , where L is an integer equal to SF max /SF min , where SF max is the maximum spread factor and SF min is the minimum spread factor, where SF max and SF min are integers, a code order number n is equal to a PN order, and wherein the second modulation matrix comprises a second set of time limited PN codes; and
P parallel outputs.
13. A PN code hopping system as in claim 12 wherein the second addressable multiplexer comprises a P:1 multiplexer.
14. A PN code hopping system as in claim 7 wherein the second address generator comprises:
a second up-down counter; and
a second look-up-table (LUT), the second LUT coupled to the second up-down counter.
15. A PN code hopping system as in claim 7 wherein the second address generator comprises a second shift register.