Granted Patent B1

US 7,130,993 · App. 10/611,175 · Granted Oct 31, 2006

Abstract

Claims (73)

1. A method comprising:

reading information on system configuration of a platform having at least a processor, a memory, a chipset, and a bus device using a firmware interface, the information including at least processor information, memory information, chipset information, and bus device information, reading the information comprising:

reading the chipset information from the chipset, and

reading the bus device information from the bus device; and

organizing the information according to a predefined format:

wherein reading the bus device information comprises:

obtaining at least a bus code, a device code, a function code, an interrupt number, and an input/output (I/O) code using a firmware interface call;

obtaining at least a device identifier, a subsystem identifier, a subsystem vendor identifier, a vendor identifier, and a device frequency from the bus device;

converting the vendor identifier to a manufacturer name; and

converting the device identifier to a device type name.

2. The method of claim 1 wherein reading the information comprises:

determining the memory information, the memory information including a memory map and a memory available amount,

determining if the firmware interface is loaded into the memory; and

reading the processor information from the processor.

3. The method of claim 2 wherein reading the processor information comprises:

obtaining at least a processor number, a processor frequency, a bus frequency, a model number, a stepping code, a revision number, a cache information, a processor identifier, and a bootstrap processor identification.

4. The method of claim 1 wherein reading the information comprises:

reading option read only memory (ROM) information from an option ROM.

5. The method of claim 1 wherein reading the chipset information comprises:

obtaining a revision number of at least one of a scaleable node controller (SNC), a scalability port switch (SPS), a server input/output hub (SIOH), and a peripheral bus hub.

6. The method of claim 1 wherein the bus device is a peripheral component interconnect (PCI) device.

7. The method of claim 1 wherein the processor is one of a 16-bit, 32-bit, and 64-bit processors.

8. The method of claim 1 wherein the platform is a multiprocessor platform.

9. An article of manufacture comprising:

a machine-accessible storage medium including data that, when accessed by a machine, causes the machine to perform operations comprising:

reading information on system configuration of a platform having at least a processor, a memory, a chipset, and a bus device using a firmware interface, the information including at least processor information, memory information, chipset information, and bus device information; wherein the data causing the machine to perform reading the information comprises data that, when accessed by the machine, causes the machine to perform operations comprising:

reading the chipset information from the chipset, and

reading the bus device information from the bus device; and

organizing the information according to a predefined format:

wherein the data causing the machine to perform reading the bus device information comprises data that, when accessed by the machine, causes the machine to perform operations comprising:

obtaining at least a bus code, a device code, a function code, an interrupt number, and an input/output (I/O) code using a firmware interface call;

obtaining at least a device identifier, a subsystem identifier, a subsystem vendor identifier, a vendor identifier, and a device frequency from the bus device;

converting the vendor identifier to a manufacturer name; and

converting the device identifier to a device type name.

10. The article of manufacture of claim 9 wherein the data causing the machine to perform reading the information comprises data that, when accessed by the machine, causes the machine to perform operations comprising:

reading option read only memory (ROM) information from an option ROM.

11. The article of manufacture of claim 9 wherein the data causing the machine to perform reading the information comprises data that, when accessed by the machine, causes the machine to perform operations comprising:

determining the memory information, the memory information including a memory map and a memory available amount,

determining if the firmware interface is loaded into the memory; and

reading the processor information from the processor.

12. The article of manufacture of claim 11 wherein the data causing the machine to perform reading the processor information comprises data that, when accessed by the machine, causes the machine to perform operations comprising:

obtaining at least a processor number, a processor frequency, a bus frequency, a model number, a stepping code, a revision number, a cache information, a processor identifier, and a bootstrap processor identification.

13. The article of manufacture of claim 9 wherein the data causing the machine to perform reading the chipset information comprises data that, when accessed by the machine, causes the machine to perform operations comprising:

obtaining a revision number of at least one of a scaleable node controller (SNC), a scalability port switch (SPS), a server input/output hub (SIOH), and a peripheral bus hub.

14. The article of manufacture of claim 9 wherein the bus device is a peripheral component interconnect (PCI) device.

15. The article of manufacture of claim 9 wherein the processor is one of a 16-bit, 32-bit, and 64-bit processors.

16. The article of manufacture of claim 9 wherein the platform is a multiprocessor platform.

17. A system comprising:

a processor;

a chipset coupled to the processor; and

a memory coupled to the processor, the memory containing instructions that, when executed by the processor cause the processor to:

read information on system configuration of the platform having at least the processor, the memory, the chipset, and a bus device using a firmware interface, the information including at least processor information, memory information, chipset information, and bus device information, wherein the instructions causing the processor to read the information comprises instructions that, when executed by the processor, cause the processor to:

read the chipset information from the chipset, and

read the bus device information from the bus device; and

organize the information according to a predefined format;

wherein the instructions causing the processor to read the bus device information comprises instructions that, when executed by the processor, cause the processor to:

obtain at least a bus code, a device code, a function code, an interrupt number, and an input/output (I/O) code using a firmware interface call;

obtain at least a device identifier, a subsystem identifier, a subsystem vendor identifier, a vendor identifier, and a device frequency from the bus device;

convert the vendor identifier to a manufacturer name; and

convert the device identifier to a device type name.

18. The system of claim 17 wherein the instructions causing the processor to read the information comprises instructions that, when executed by the processor, cause the processor to:

determine the memory information, the memory information including a memory map and a memory available amount,

determine if the firmware interface is loaded into the memory; and

read the processor information from the processor.

19. The system of claim 18 wherein the instructions causing the processor to read the processor information comprises instructions that, when executed by the processor, cause the processor to:

obtain at least a processor number, a processor frequency, a bus frequency, a model number, a stepping code, a revision number, a cache information, a processor identifier, and a bootstrap processor identification.

20. The system of claim 17 wherein the instructions causing the processor to read the information comprises instructions that, when executed by the processor, cause the processor to:

read option read only memory (ROM) information from an option ROM.

21. The system of claim 17 wherein the instructions causing the processor to read the chipset information comprises instructions that, when executed by the processor, cause the processor to:

obtain a revision number of at least one of a scaleable node controller (SNC), a scalability port switch (SPS), a server input/output hub (SIOH), and a peripheral bus hub.

22. The system of claim 17 wherein the bus device is a peripheral component interconnect (PCI) device.

23. The system of claim 17 wherein the processor is one of a 16-bit, 32-bit, and 64-bit processors.

24. The system of claim 17 wherein the platform is a multiprocessor platform.

Assignments (13)