Processing circuit and method for variable-length coding and decoding

1. A variable-length encode/decode processor, comprising:

a central processing unit;

a special-purpose processing unit coupled to the central processing unit and operable to process image data according to a block-based coding/decoding standard; and

an input/output buffer coupled to the special-purpose processing unit and operable to transfer the image data between the special-purpose processing unit and an input/output bus;

wherein the special-purpose processing unit is operable to:

address a memory location with a value stored in a symbol register;

retrieve an address from the addressed location; and

store the retrieved address in the symbol register.

2. The processor of claim 1 wherein the special-purpose processing unit is operable to perform a per byte bit reversal on bytes of the image data received from the input/output buffer.

3. The processor of claim 1 wherein the special-purpose processing unit is operable to parse the image data received from the input/output buffer according to an MPEG format.

4. The processor of claim 1 wherein the special-purpose processing unit is operable to selectively perform a per byte bit reversal on the image data and to provide the reversed bytes of image data to the input/output buffer.

5. The processor of claim 1 wherein the special-purpose processing unit is operable to:

provide a stream of the image data to the input/output buffer, the image data representing pixels of an image; and

selectively splice into the stream other data.

6. The processor of claim 1 wherein the special-purpose processing unit is operable to:

provide a stream of the image data to the input/output buffer, the image data representing pixels of a first image; and

selectively splice into the stream image data representing pixels of a second image.

7. The processor of claim 1 wherein the special-purpose processing unit is operable to process multiple streams of the image data by:

processing a first stream of image data;

saving a first machine state associated with the first stream;

processing a second stream of the image data after saving the first machine state;

restoring the first machine state; and

continuing to process the first stream after restoring the first machine state.

8. The processor of claim 1 wherein the special-purpose processing unit comprises a get-bits processing unit.

9. A variable-length encode/decode processor, comprising:

a central processing unit;

a special-purpose processing unit coupled to the central processing unit and operable to process image data according to a block-based coding/decoding standard;

an input/output buffer coupled to the special-purpose processing unit and operable to transfer the image data between the special-purpose processing unit and an input/output bus; and

a symbol register coupled to the special-purpose processing unit and to the input/output buffer;

wherein the special-purpose processing unit is operable to:

address a memory location with a value stored in the symbol register;

retrieve an address from the addressed location;

store the retrieved address in the symbol register.

10. The processor of claim 9 wherein the special-purpose processing unit is operable to:

receive a stream of image data from the input/output buffer; shift in the image data; and

store the first sixteen bits of the image data in the symbol register.

11. The processor of claim 9 wherein the special-purpose processing unit is operable to:

address a memory location with a value stored in the symbol register;

retrieve data from the addressed location;

shift the retrieved data; and

provide the shifted data to the input/output buffer.

12. The processor of claim 9 wherein the special-purpose processing unit is operable to:

address a memory location with a value stored in the symbol register;

retrieve a byte of data from the addressed location;

reverse the bits of the retrieved byte; and

provide the bit-reversed byte of data to the input/output buffer.

13. A variable-length encode/decode processor, comprising:

a central processing unit;

a special-purpose processing unit coupled to the central processing unit and operable to process image data according to a block-based coding/decoding standard;

at least one shared register coupled to the central processing unit and to the special-purpose processing unit;

at least one memory unit coupled to the central processing unit and to the special-purpose processing unit and operable to store an image; and

a symbol register coupled to the special-purpose processing unit, the shared register, and the memory unit;

wherein the special-purpose processing unit is operable to:

form a first address from respective values stored in the symbol register and in the shared register;

retrieve a value from a location of the memory unit, the location having the first address; and

store the retrieved value in the symbol register.

14. A variable-length encode/decode processor comprising:

a central processing unit;

a special-purpose processing unit coupled to the central processing unit and operable to process image data according to a block-based coding/decoding standard;

at least one shared register coupled to the central processing unit and to the special-purpose processing unit;

at least one memory unit coupled to the central processing unit and to the special-purpose processing unit and operable to store an image; and

a symbol register coupled to the special-purpose processing unit, the shared register, and the memory unit;

wherein the special-purpose processing unit includes a general-purpose register and is operable to:

form a first address from respective values stored in the symbol register and in the general-purpose register;

retrieve a value from a location of the memory unit, the location having the first address; and

store the retrieved value in the symbol register.

15. A variable-length encode/decode processor, comprising:

a central processing unit;

a special-purpose processing unit coupled to the central processing unit and operable to process image data according to a block-based coding/decoding standard;

at least one shared register coupled to the central processing unit and to the special-purpose processing unit;

at least one memory unit coupled to the central processing unit and to the special-purpose processing unit and operable to store an image; and

a symbol register coupled to the special-purpose processing unit, the shared register, and the memory unit;

wherein the special-purpose processing unit includes a general-purpose register and is operable to:

form a first address from respective values stored in the symbol register and in the general-purpose register;

retrieve a second address from a location of the memory unit having the first address, the second address corresponding to another location of the memory unit that stores a portion of an image; and

store the second address in the symbol register.

16. A method for image processing, comprising:

receiving a first stream of data that represents a first version of an image:

processing the first stream of data with a special-purpose processor under the control of a central processing unit;

returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit; and

generating a second stream of data that represents a second version of the image;

wherein returning the state of the special-purpose processor comprises storing in the shared register an address that points to the state.

17. The method of claim 16 further comprising returning multiple states of the special-purpose processor to the central processing unit via respective registers shared by the special-purpose processor and the central processing unit.

18. A method for image processing, comprising:

receiving a first stream of data that represents a first version of an image;

processing the first stream of data with a special-purpose processor under the control of a central processing unit;

returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit; and

generating a second stream of data that represents a second version of the image;

wherein processing the first data stream comprises processing the first data stream with an arithmetic logic unit in the special-purpose processor; and

returning the state of the special-purpose processor comprises storing a result generated by the arithmetic logic unit in the shared register.

19. A method for image processing, comprising:

receiving a first stream of data that represents a first version of an image;

processing the first stream of data with a special-purpose processor under the control of a central processing unit;

returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit; and

generating a second stream of data that represents a second version of the image;

wherein returning the state of the special-purpose processor comprises storing a testable machine state of the special-purpose processor in the shared register.

20. A method for image processing, comprising:

receiving a first stream of data that represents a first version of an image;

processing the first stream of data with a special-purpose processor under the control of a central processing unit;

returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit; and

generating a second stream of data that represents a second version of the image;

wherein:

processing the first data stream comprises adding one to bits eleven to fifteen of a load value stored in a memory to generate a sum; and

returning the state of the special-purpose processor comprises storing the sum in the shared register.

21. A method for image processing, comprising:

receiving a first stream of data that represents a first version of an image;

processing the first stream of data with a special-purpose processor under the control of a central processing unit;

returning a state of the spccial-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit; and

generating a second stream of data that represents a second version of the image;

wherein returning the state of the special-purpose processor comprises storing the first sixteen bits of the first data stream in the shared register.

22. A method for image processing, comprising:

receiving a first stream of data that represents a first version of an image;

processing the first stream of data with a special-purpose processor under the control of a central processing unit;

returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit; and

generating a second stream of data that represents a second version of the image;

wherein returning the state of the special-purpose processor comprises storing in the first shared register a count of the leading zeros or leading ones in a second register that is shared by the special-purpose processor and the central processing unit.

23. A method for image processing, comprising:

receiving a first stream of data that represents a first version of an image;

processing the first stream of data with a special-purpose processor under the control of a central processing unit;

returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit; and

generating a second stream of data that represents a second version of the image;

wherein processing with a special-purpose processor comprises processing the first data stream with a get-bits processing unit.

24. A method for image processing, comprising:

receiving a first stream of data that represents a first version of an image;

processing the first stream of data with a special-purpose processor under the control of a central processing unit;

returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit; and

generating a second stream of data that represents a second version of the image;

wherein returning a state further comprises:

forming a first address from respective values stored in a symbol register and in the first register;

retrieving the state from a location of memory, the location having the first address; and

storing the retrieved state in the symbol register.

25. A method for image pfpcessing, comprising:

receiving a first stream of data that represents a first version of an image;

processing the first stream of data with a special-purpose processor under the control of a central processing unit;

returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processin unit; and

generating a second stream of data that represents a second version of the image;

wherein returning a state further comprises:

forming a first address from respective values stored in a symbol register and in a general-purpose register in the special-purpose processor;

retrieving the state from a location of memory, the location having the first address; and

storing the retrieved state in the symbol register.

26. A method for image processing, comprising:

receiving a first stream of data that represents a first version of an image; processing the first stream of data with a special-purpose processor under the control of a central processing unit;

returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit; and

generating a second stream of data that represents a second version of the image;

wherein returning a state further comprises:

forming a first address from respective values stored in a symbol register and in a general-purpose register in the special-purpose processor; and

storing the first address in the symbol register.