IP Library Granted Patent US 7,346,480
Granted Patent B1
US 7,346,480 · App. 10/611,314 · Granted Mar 18, 2008

Impedance mismatch modeling in a data flow or discrete time based system simulation

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Quick Facts
Patent No.
US 7,346,480
App. No.
10/611,314
Granted
Mar 18, 2008
Kind
B1
Abstract

This invention provides directional connectivity described by the interconnections of the blocks in the schematic or netlist that are used to propagate impedance data from one block to another. The propagation of impedance data for discrete time based simulation programs allow for the simulation under less than ideal termination conditions between the blocks. This invention also supports functionality where the input impedance and output impedance of each block are not perfectly terminated. This assumption can lead to very significant modeling errors in the simulated results. In general, termination impedances are complex frequency dependent functions that result in frequency dependent mismatch losses between the blocks. This invention allows for the propagation and calculation of impedance mismatches between the various blocks.

Claims (26)

1. A system simulator for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs, comprising:

obtaining impedance values for output impedance of a first source block during reverse propagation, obtaining impedance value for input impedance of a second source block during forward propagation and impedance value for input impedance of a third source block during forward propagation by a property propagation methodology;

calculating in a microprocessor impedance value for input impedance of the first source block during forward propagation from the values for input impedance of the second source block, input impedance from the third source block during forward propagation and back propagating the value or input impedance to an input node for the first source block during forward propagation;

calculating in the microprocessor impedance values for output impedance of the first source block in reverse propagation from the values for input impedance from the first source block during forward propagation, input impedance from the third source block during forward propagation and back propagating the value of the output impedance of the first source block during reverse propagation to an output node for the first source block;

calculating in the microprocessor impedance values for output impedance of the third source block during reverse propagation from the values for input impedance from the first source block during forward propagation, input impedance from the second source block during forward propagation and back propagating the value of the output impedance of the third source block during reverse propagation to an output node for the first source block;

propagating the impedance values for output impedance of the second source block during reverse propagation and the new impedance value of output impedance of to the third source block during reverse propagation; and

calculating in the microprocessor a value for impedance mismatch for the first source block, a value for impedance mismatch for the second source block and a value for impedance mismatch for the third source block.

2. The system simulator for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 1 , further comprising calculating a minimum and a maximum operating frequency values for the source block.

3. The system simulator for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 2 , further comprising storing the minimum and maximum operating frequency values of the source block in the system simulator.

4. The system simulator system for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 3 , further comprising determining on each propagation pass whether a new minimum or a new maximum operating frequency value obtained from the propagation pass is less the minimum operating frequency value or more than the maximum operating frequency value that is stored in the system simulator, and if so, updating the stored minimum operating frequency value with the new minimum operating frequency value and updating the stored maximum operating frequency value with the new maximum operating frequency value.

5. The system simulator system for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 4 , further comprising generating a global mismatch frequencies from a discrete set of frequencies having a range of resolution between the minimum operating frequency value and maximum operating frequency value.

6. The system simulator system for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 5 , where the global mismatch frequencies are complex, frequency dependent values.

7. The system simulator system for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 5 , further comprising calculating corrections values on the source block input signal.

8. A system simulator for calculating the impedance mismatch of a source block having a plurality of inputs and at least one outputs, comprising:

obtaining impedance values of output impedance of a first source block during reverse propagation, impedance value of output impedance from a second source block during reverse propagation and impedance value of input impedance from a third source block during forward propagation by a property propagation methodology;

calculating in a microprocessor impedance value of input impedance of the first source block during forward propagation from the values for input impedance from the second source block during forward propagation, input impedance from the third source block during forward propagation and back propagating the value of input impedance of the first source block during forward propagation to an input node for the first source block;

calculating in the microprocessor impedance values for input impedance of the first source block during forward propagation from the values for output impedance from the first source block during reverse propagation, input impedance from the third source block during forward propagation and back propagating the value of input impedance from the second source block during forward propagation to an output node for the first source block;

calculating in the microprocessor impedance values for output impedance of the first source block during reverse propagation from the values for output impedance from the first source block during reverse propagation, output impedance from the second source block during reverse propagation and back propagating the value of output impedance of the third source block during reverse propagation to an output node for the first source block;

propagating the impedance values for output impedance of the second source block during reverse propagation and the new impedance value output impedance of the third source block during reverse propagation; and

calculating in the microprocessor values for a first impedance mismatch and a second impedance mismatch for the first source block, and a value for impedance mismatch for the third source block.

9. The system simulator for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 8 , further comprising calculating a minimum and a maximum operating frequency values for the source block.

10. The system simulator for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 9 , further comprising storing the minimum and maximum operating frequency values of the source block in the system simulator.

11. The system simulator system for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 10 , further comprising determining on each propagation pass whether a new minimum or a new maximum operating frequency value obtained from the propagation pass is less the minimum operating frequency value or more than the maximum operating frequency value that is stored in the system simulator, and if so, updating the stored minimum operating frequency value with the new minimum operating frequency value and updating the stored maximum operating frequency value with the new maximum operating frequency value.

12. The system simulator system for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 11 , further comprising generating a global mismatch frequencies from a discrete set of frequencies having a range of resolution between the minimum operating frequency value and maximum operating frequency value.

13. The system simulator system for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 12 , where the global mismatch frequencies are complex, frequency dependent values.

14. The system simulator system for calculating the impedance mismatch of a source block having at least one input and a plurality of outputs of claim 13 , further comprising calculating corrections values on the source block input signal.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2024
From: AWR LLC
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 066414/0891 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 052935/0001) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
Reel/Frame 065653/0463 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 057280/0028) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 065231/0466 →
SECURITY INTEREST Recorded Jun 18, 2021
From: NATIONAL INSTRUMENTS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 057280/0028 →
SECURITY INTEREST Recorded Jun 14, 2020
From: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 052935/0001 →
MERGER Recorded Nov 3, 2011
From: APPLIED WAVE RESEARCH, INC.
To: APPLIED WAVE RESEARCH, INC.
Reel/Frame 027167/0187 →
CHANGE OF NAME Recorded Nov 3, 2011
From: APPLIED WAVE RESEARCH, INC.
To: AWR CORPORATION
Reel/Frame 027170/0950 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2004
From: PEKAREK, JOSEPH EDWARD; SANTOS, ALBERT; HUDSON, SCOTTY
To: APPLIED WAVE RESEARCH, INC.
Reel/Frame 014916/0365 →