System and method for packet transmission from fragmented buffer
View Patent ↗The present invention is directed to methods and systems for implementing a DMA scheduling mechanism and a DMA system for transmission from fragmented buffers. According to an aspect of the present invention, a processor controls several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. According to another aspect of the present invention, a system for handling transmission of network packets which are assembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.
1. A method for transferring network packet data that is stored in memory to an output device, the method comprising the steps of:
concatenating one or more packet data octets from at least a first data word having at least one packet data octet to be included in a network packet to generate a first sequence of packet data octets having an octet length at least as great as an octet length of a data word;
storing the first sequence of packet data octets in a FIFO buffer operably connected to the output device when the octet length of the sequence of packet data octets is equal to the octet length of a data word; and
storing a first subset of packet data octets from the first sequence of packet data octets in the FIFO buffer and storing a remaining second subset of packet data octets from the first sequence in an alignment register when the octet length of the first sequence of packet data octets exceeds the octet length of a data word, wherein an octet length of the first subset of packet data octets is equal to the octet length of a data word, wherein data received at the alignment register is received from a direct memory access (DMA) component.
2. The method as in claim 1 , further comprising the step of storing the first sequence of packet data octets in the alignment register when the octet length of the first sequence of packet data octets is less than the octet length of a data word.
3. The method as in claim 1 , further comprising the steps of:
concatenating at least one packet data octet from a second data word accessed from memory with the second subset of packet data octets stored in the alignment register to generate a second sequence of packet data octets having a octet length at least as great as the octet length of a data word;
storing the second sequence of packet data octets in the FIFO buffer when the octet length of the sequence of packet data octets is equal to the octet length of a data word; and
storing a first subset of packet data octets from the second sequence of packet data octets in the FIFO buffer and storing a remaining second subset of packet data octets from the second sequence the alignment register when the octet length of the second sequence of packet data octets exceeds the octet length of a data word, wherein an octet length of the first subset of packet data octets of the second sequence is equal to the octet length of a data word.
4. The method as in claim 1 , wherein the octet length of a data word is an integer multiple of four.
5. A system for transferring network packet data stored in memory to an output device, the system comprising:
a direct memory access (DMA) interface for accessing a set of data words stored in memory, each data word having at least one valid octet to be included in a network packet and each data word being accessed using a DMA address associated with the data word;
a first in-first out (FIFO) buffer for storing network packet data to be transmitted by the output device; and
an alignment block having at least one alignment register, wherein the alignment register for storing at least one data octet, and wherein the alignment block is adapted to:
concatenate one or more packet data octets from at least a first data word having at least one packet data octet to be included in a network packet to generate a first sequence of packet data octets having an octet length at least as great as an octet length of a data word;
store the first sequence of packet data octets in a FIFO buffer operably connected to the output device when the octet length of the sequence of packet data octets is equal to the octet length of a data word; and
store a first subset of packet data octets from the first sequence of packet data octets in the FIFO buffer and store a remaining second subset of packet data octets from the first sequence in an alignment register when the octet length of the first sequence of packet data octets exceeds the octet length of a data word, wherein an octet length of the first subset of packet data octets is equal to the octet length of a data word.
6. The system as in claim 5 , wherein the alignment block is further adapted to store the first sequence of packet data octets in the alignment register when the octet length of the first sequence of packet data octets is less than the octet length of a data word.
7. The system as in claim 5 , wherein the alignment block is further adapted to:
concatenate at least one packet data octet from a second data word accessed from memory with the second subset of packet data octets stored in the alignment register to generate a second sequence of packet data octets having a octet length at least as great as the octet length of a data word;
store the second sequence of packet data octets in the FIFO buffer when the octet length of the sequence of packet data octets is equal to the octet length of a data word; and
store a first subset of packet data octets from the second sequence of packet data octets in the FIFO buffer and storing a remaining second subset of packet data octets from the second sequence the alignment register when the octet length of the second sequence of packet data octets exceeds the octet length of a data word, wherein an octet length of the first subset of packet data octets of the second sequence is equal to the octet length of a data word.
8. The system as in claim 5 , wherein the octet length of a data word is an integer multiple of four.
9. The system as in claim 5 , wherein the alignment block further includes at least one FIFO register and is further adapted to store at least a third sequence of one or more packet data octets from a processor in the FIFO register.
10. The system as in claim 9 , wherein the alignment block is further adapted to store the third sequence of packet data octets in the FIFO buffer when an octet length of the third sequence is equal to the octet length of a data word.
11. The system as in claim 9 , wherein the alignment block is further adapted to concatenate at least a subset of the third sequence of packet data octets with a sequence of packet data octets stored in the alignment register to generate a fourth sequence of packet data octets and store the fourth sequence of packet data octets in the FIFO buffer when an octet length of the fourth sequence is equal to the octet length of a data word.
12. The system as in claim 9 , wherein the alignment block is further adapted to concatenate at least a subset of the third sequence of packet data octets with a sequence of packet data octets stored in the alignment register to generate a fourth sequence of packet data octets and store a first subset the fourth sequence of packet data octets in the FIFO buffer and a remaining second subset of the fourth sequence of packet at octets in the alignment register when an octet length of the fourth sequence exceeds the octet length of a data word.
13. The system as in claim 9 , wherein the alignment block is further adapted to concatenate at least a subset of the third sequence of packet data octets with a sequence of packet data octets stored in the alignment register to generate a fourth sequence of packet data octets and store the fourth sequence of packet data octets in the alignment register when an octet length of the fourth sequence is less than the octet length of a data word.
14. A system for transferring network packet data stored in memory to an output device, the system comprising:
means for accessing a set of data words stored in memory, each data word having at least one valid octet to be included in a network packet and each data word being accessed using a DMA address associated with the data word;
means for concatenating one or more of the at least one packet data octet having at least one packet data octet to be included in a network packet to generate a first sequence of packet data octets having an octet length at least as great as an octet length of a data word;
means for storing the first sequence of packet data octets in a FIFO buffer operably connected to the output device when the octet length of the sequence of packet data octets is equal to the octet length of a data word; and
means for storing a first subset of packet data octets from the first sequence of packet data octets in the FIFO buffer and storing a remaining second subset of packet data octets from the first sequence in an alignment register when the octet length of the first sequence of packet data octets exceeds the octet length of a data word, wherein an octet length of the first subset of packet data octets is equal to the octet length of a data word.
15. The system as in claim 14 , further comprising means for storing the first sequence of packet data octets when the octet length of the first sequence of packet data octets is less than the octet length of a data word.
16. The system as in claim 14 , further comprising means for concatenating at least one packet data octet from a second data word accessed from memory with the second subset of packet data octets to generate a second sequence of packet data octets having a octet length at least as great as the octet length of a data word.
17. The system as in claim 16 , further comprising means for storing the second sequence of packet data octets when the octet length of the sequence of packet data octets is equal to the octet length of a data word.
18. The system as in claim 17 , further comprising means for storing a first subset of packet data octets from the second sequence of packet data octets in the FIFO buffer.
19. The system as in claim 18 , further comprising means for storing a remaining second subset of packet data octets from the second sequence the alignment register when the octet length of the second sequence of packet data octets exceeds the octet length of a data word, wherein an octet length of the first subset of packet data octets of the second sequence is equal to the octet length of a data word.
20. The system as in claim 14 , wherein the octet length of a data word is an integer multiple of four.