Amplifying circuit with variable load drivability
View Patent ↗The present invention relates to an amplifying circuit that can change load drivability responding to load conditions, and reduce power consumption. The amplifying circuit according to the present invention comprises an amplifying means that amplifies input signals a first time to generate a first and a second amplified signals through a first and a second transistors, and further amplifies the first and second amplified signals once again through a third and a fourth transistors, for final outputs; a detecting means for detecting the first and second amplified signals from the amplifying means and generating a first and a second detection signals; and a load drivability control means that is controlled by the first and second detection signals from the detecting means to change load drivability of the amplifying means.
1. An Amplifying circuit with variable load drivability, comprising:
an amplifying means for amplifying input signals a first time through a first and a second transistors to generate first and second amplified signals and amplifying the first and second amplified signals a second time through a third and a fourth transistors to generate output signals;
a detecting means for detecting the first and second amplified signals from said amplifying means to generate a first and a second detection signals; and
a load drivability control means controlled by the first and second detection signals outputted from the detecting means for changing load drivability of the amplifying means,
wherein the detecting means further includes:
a Schmitt-trigger means for detecting voltage level change in the first and second amplified signals;
an exclusive OR gate for receiving output signals from said Schmitt-trigger means to generate the first detection signal; and
an inverter for inverting the first detection signal to generate the second detection signal.
2. The amplifying circuit with variable load drivability as recited in claim 1 , wherein said first arid second Schmitt-trigger means output a low level signal at ground level if said first and second amplified signals reach input signal level of said first transistor, and outputs a high level signal of source voltage if said first and second amplified signals reach input signal level of said second transistor.
3. The amplifying circuit with variable load drivability as recited in claim 1 , wherein said load drivability control includes:
a first control means that is driven by said second detection signal of said detecting means and increases drivability of said third transistor of said amplifying means; and
a second control means that is driven by said first detection signal of said detecting means and increases drivability of said fourth transistor of said amplifying means.
4. The amplifying circuit with variable load drivability as recited in claim 3 , wherein the first control means includes:
a fifth transistor that increases load drivability in cooperation with said third transistor of said amplifying means;
a sixth transistor that disables said fifth transistor in response to said second detection signal; and
a seventh transistor that delivers said first amplified signals to gate input of said fifth transistor in response to said second detection signal.
5. The amplifying circuit with variable load drivability as recited in claim 4 , wherein said fifth transistor of said first control means and said third transistor of said amplifying means comprise PMOS transistors, and said fifth transistor has a size not less than four (4) times that of said third transistor.
6. The amplifying circuit with variable load drivability as recited in claim 4 , wherein said sixth transistor and seventh transistors of said first control means comprise respectively a PMOS transistor and a NMOS transistor, both receiving said second detection signal as gate inputs.
7. The amplifying circuit with variable load drivability as recited in claim 3 , wherein said second control means includes:
an eighth transistor that increases load drivability in cooperation with said fourth transistor of said amplifying means;
a ninth transistor that disables said eighth transistor in response to said second detection signals; and
a tenth transistor that delivers said second amplified signal to a gate input of said eighth transistor in response to said second detection signal.
8. The amplifying circuit with variable load drivability as recited in claim 7 , wherein said eighth transistor of said second control means and said fourth transistor of said amplifying means comprise NMOS transistors, and said eighth transistor has a size not less than four times that of said fourth transistor.
9. The amplifying circuit with variable load drivability as recited in claim 7 , wherein said ninth and tenth transistors of said second control means respectively comprise a PMOS transistor and an NMOS transistor, both receiving said second detection signal as gate inputs.
10. An Amplifying circuit with variable load drivability, comprising:
an amplifying means for amplifying input signals a first time through a first and a second transistors to generate first and second amplified signals and the first and second amplified signals a second time through a third and a fourth transistors to generate output signals;
a detecting means for detecting the first and second amplified signals from said amplifying means to generate a first and a second detection signals; and
a load drivability control means controlled by the first and second detection signals outputted from the detecting means for changing load drivability of the amplifying means,
wherein said load drivability control includes:
a first control means that is driven by said second detection signal of said detecting means and increases drivability of said third transistor of said amplifying means; and
a second control means that is driven by said first detection signal of said detecting means and increases drivability of said fourth transistor of said amplifying means;
wherein the first control means includes:
a fifth transistor that increases load drivability in cooperation with said third transistor of said amplifying means;
a sixth transistor that disables said fifth transistor in response to said second detection signal; and
a seventh transistor that delivers said first amplified signals to gate input of said fifth transistor in response to said second detection signal.
11. The amplifying circuit with variable load drivability as recited in claim 10 , wherein said fifth transistor of said first control means and said third transistor of said amplifying means comprise PMOS transistors, and said fifth transistor has a size not less than four (4) times that of said third transistor.
12. The amplifying circuit with variable load drivability as recited in claim 10 , wherein said sixth transistor and seventh transistors of said first control means comprise respectively a PMOS transistor and a NMOS transistor, both receiving said second detection signal as gate inputs.
13. An Amplifying circuit with variable load drivability, comprising:
an amplifying means for amplifying input signals a first time through a first and a second transistors to generate first and second amplified signals and the first and second amplified signals a second time through a third and a fourth transistors to generate output signals;
a detecting means for detecting the first and second amplified signals from said amplifying means to generate a first and a second detection signals; and
a load drivability control means controlled by the first and second detection signals outputted from the detecting means for changing load drivability of the amplifying means,
wherein said load drivability control includes:
a first control means that is driven by said second detection signal of said detecting means and increases drivability of said third transistor of said amplifying means; and
a second control means that is driven by said first detection signal of said detecting means and increases drivability of said fourth transistor of said amplifying means;
wherein said second control means includes:
an eighth transistor that increases load drivability in cooperation with said fourth transistor of said amplifying means;
a ninth transistor that disables said eighth transistor in response to said second detection signals; and
a tenth transistor that delivers said second amplified signal to a gate input of said eighth transistor in response to said second detection signal.
14. The amplifying circuit with variable load drivability as recited in claim 13 , wherein said eighth transistor of said second control means and said fourth transistor of said amplifying means comprise NMOS transistors, and said eighth transistor has a size not less than four times that of said fourth transistor.
15. The amplifying circuit with variable load drivability as recited in claim 13 , wherein said ninth and tenth transistors of said second control means respectively comprise a PMOS transistor and an NMOS transistor, both receiving said second detection signal as gate inputs.