Transimpedance amplifier
A transimpedance amplifier, which is useful as an optical fiber preamplifier, is disclosed. The illustrative embodiment exhibits four characteristics. First, it minimizes the equivalent input noise current. Second, it has a wide bandwidth. Third, it has a reasonably large output voltage, and fourth, it is stable over wide temperature and voltage ranges. The illustrative embodiment comprises a transimpedance stage and a gain stage. Both stages employ a pure NMOS design which contributes to the above four advantages. Bandwidth is further increased over the prior art by the use of inductive loads. The inductive loads of the illustrative embodiment are not physical inductors, but transistor-based “active” inductors: the combination of a resistor connected in series with the gate of an NMOS transistor.
1. An apparatus comprising:
a first transistor having a gate terminal, a drain terminal, and a source terminal;
a first resistor having a first terminal and second terminal, wherein said first terminal of said first resistor is electrically connected to said gate terminal of said first transistor;
a second transistor having a gate terminal, a drain terminal, and a source terminal, wherein said drain terminal of said second transistor is electrically connected to said source terminal of said first transistor; and
a second resistor having a first and a second terminal, wherein said first terminal of said second resistor is electrically connected to said gate terminal of said second transistor, and wherein said second terminal of said second resistor is electrically connected to said drain terminal of said first transistor;
wherein a first voltage connected to said second terminal of said first resistor is greater than a second voltage connected to said drain terminal of said first transistor by at least the gate-to-source threshold voltage of said first transistor.
2. An apparatus comprising:
a first transistor having a gate terminal, a drain terminal, and a source terminal;
a first resistor having a first terminal and second terminal, wherein said first terminal of said first resistor is electrically connected to said gate terminal of said first transistor;
a second transistor having a gate terminal, a drain terminal, and a source terminal, wherein said drain terminal of said second transistor is electrically connected to said source terminal of said first transistor; and
a second resistor having a first and a second terminal, wherein said first terminal of said second resistor is electrically connected to said gate terminal of said second transistor, and wherein said second terminal of said second resistor is electrically connected to said drain terminal of said first transistor;
wherein said first transistor further comprises a first substrate terminal and said second transistor further comprises a second substrate terminal wherein said first substrate terminal and said second substrate terminal are electrically connected to each other.
3. The apparatus of claim 2 wherein said first substrate is connected to a ground voltage.
4. The apparatus of claim 2 further comprising:
a third resistor having a first and second terminals, wherein said first terminal of said third resistor is electrically connected to said source terminal of said second transistor and said second terminal of said third resistor is electrically connected to said substrate of said first transistor;
a third transistor having a gate terminal, drain terminal, source terminal, and substrate terminal, wherein said drain terminal of said third transistor is electrically connected to said gate terminal of said second transistor, and wherein said substrate terminal of said third transistor is electrically connected to said source terminal of said third transistor and to said substrate terminal of said first transistor.
5. The apparatus of claim 4 wherein said first transistor, said second transistor, and said third transistor are n-type enhancement mode field effect transistors.
6. An apparatus comprising:
a first transistor having a gate terminal, a drain terminal, and source terminal;
a second transistor having a gate terminal, a drain terminal, and a source terminal, wherein said source terminal of said first transistor is electrically connected to said drain terminal of said second transistor;
a first resistor having a first terminal and second terminal, wherein said first terminal of said first resistor is electrically connected to said gate terminal of said first transistor;
a second resistor having a first terminal and second terminal, wherein said first terminal of said second resistor is electrically connected to said drain terminal of said second transistor, and wherein said second terminal of said second resistor is electrically connected to said gate terminal of said second transistor;
a third transistor having a gate terminal, a drain terminal, and a source terminal, wherein said source terminal of said third transistor is electrically connected to said source terminal of said second transistor, and wherein said drain terminal of said third transistor is electrically connected to said first terminal of said second resistor;
a fourth transistor having a gate terminal, a drain terminal, and a source terminal, wherein said source terminal of said fourth transistor is electrically connected to said drain terminal of said third transistor, and wherein said drain terminal of said fourth transistor is electrically connected to said drain terminal of said first transistor; and
a third resistor having a first terminal and second terminal, wherein said first terminal of said third resistor is electrically connected to said gate terminal of said fourth transistor, and wherein said second terminal of said third resistor is electrically connected to said second terminal of said first resistor.
7. An apparatus comprising:
a first transistor having a gate terminal, a drain terminal, and source terminal;
a second transistor having a gate terminal, a drain terminal, and a source terminal, wherein said source terminal of said first transistor is electrically connected to said drain terminal of said second transistor;
a first resistor having a first terminal and second terminal, wherein said first terminal of said first resistor is electrically connected to said gate terminal of said first transistor; and
a second resistor having a first terminal and second terminal, wherein said first terminal of said second resistor is electrically connected to said drain terminal of said second transistor, and wherein said second terminal of said second resistor is electrically connected to said gate terminal of said second transistor;
wherein a first voltage connected to said second terminal of said first resistor is greater than a second voltage connected to said drain terminal of said first transistor by at least the gate-to-source threshold voltage of said first transistor.
8. The apparatus of claim 6 :
wherein said first transistor further comprises a substrate terminal,
wherein said second transistor further comprises a substrate terminal,
wherein said third transistor further comprises a substrate terminal,
wherein said fourth transistor further comprises a substrate terminal,
wherein said substrate terminal of said first transistor is electrically connected to said source terminal of said second transistor,
wherein said substrate terminal of said second transistor is electrically connected to said source terminal of said second transistor,
wherein said substrate terminal of said third transistor is electrically connected to said source terminal of said third transistor, and
wherein said substrate terminal of said fourth transistor is electrically connected to said source terminal of said third transistor.
9. The apparatus of claim 8 wherein said first substrate is connected to a ground voltage.
10. The apparatus of claim 8 further comprising
a fifth transistor having a gate terminal, a drain terminal, a source terminal, and a substrate terminal, wherein said drain terminal of said fifth transistor is electrically connected to said gate terminal of said third transistor, and wherein said substrate terminal of said fifth transistor is electrically connected to said source terminal of said third transistor;
a sixth transistor having a gate terminal, a drain terminal, a source terminal, and a substrate terminal, wherein said drain terminal of said sixth transistor is electrically connected to said drain terminal of said fourth transistor, wherein said source terminal of said sixth transistor is electrically connected to said drain terminal of said fifth transistor, and wherein said substrate terminal of said sixth transistor is electrically connected to said source terminal of said fifth transistor; and
a fourth resistor having a first terminal and a second terminal, wherein said first terminal of said fourth resistor is electrically connected to said gate terminal of said sixth transistor, and wherein said second terminal of said fourth resistor is electrically connected to said second terminal of said first resistor.
11. The apparatus of claim 10 further comprising
a seventh transistor having a gate terminal, a drain terminal, a source terminal, and a substrate terminal, wherein said source terminal of said seventh transistor is electrically connected to said source terminal of said second transistor, wherein said gate terminal of said seventh transistor is electrically connected to said drain terminal of said second transistor, and wherein said substrate terminal of said seventh transistor is electrically connected to said source terminal of said seventh transistor; and
a fifth resistor having a first terminal and second terminal, wherein said first terminal of said fifth resistor is electrically connected to said drain terminal of said seventh transistor, and wherein said second terminal of said fifth resistor is electrically connected to said drain terminal of said fourth transistor.
12. The apparatus of claim 11 wherein said first transistor, said second transistor, said third transistor, said fourth transistor, said fifth transistor, said sixth transistor, and said seventh transistor are n-type enhancement mode field effect transistors.
13. The apparatus of claim 12 wherein said source terminal of said second transistor is connected to a ground voltage.