Thin film transistor array panel including storage electrode
View Patent ↗A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate; a plurality of storage conductors formed on the substrate, each storage conductor including a plurality of branches; a gate insulating layer formed on the gate line and the storage conductor; a semiconductor layer formed on the gate insulating layer; a data conductor formed on the semiconductor layer; a passivation layer formed on the data conductor; and a pixel electrode formed on the passivation layer, wherein at most one of the branches of each storage conductor has an isolated end.
1. A thin film transistor array panel, comprising:
an insulating substrate;
a gate line formed on the substrate;
a plurality of storage electrodes formed on the substrate, each storage
electrode including a plurality of branches, wherein one of the branches has an isolated end and the remaining branches form a closed loop, and wherein the isolated end is electrically connected by a connector to a storage electrode line formed on the substrate;
a gate insulating layer formed on the gate line and the storage electrode;
a semiconductor layer formed on the gate insulating layer;
a data conductor formed on the semiconductor layer;
a passivation layer formed on the data conductor; and
a pixel electrode layer formed on the passivation layer.
2. The thin film transistor array panel of claim 1 , wherein adjacent storage electrodes are connected by connecting portions.
3. The thin film transistor array panel of claim 1 , wherein the connector is a connection bridge having a portion thereof connected to the isolated end of each of the plurality of storage electrodes and a portion thereof connected to storage electrode line formed on the substrate.
4. The thin film transistor array panel of claim 1 , wherein the plurality of branches of each storage electrode further comprises two longitudinal branches connected to two oblique branches to form the closed loop.
5. The thin film transistor array panel of claim 1 , wherein each storage electrode comprises two longitudinal branches connected to three oblique branches, the connected branches forming two closed loops.
6. The thin film transistor array panel of claim 1 , wherein each storage electrode comprises two longitudinal branches connected to four oblique branches, the connected branches forming three closed loops.
7. The thin film transistor array panel of claim 1 , wherein the pixel electrode has a plurality of cutouts, and at least one of the cutouts overlaps the storage electrode.
8. The thin film transistor panel of claim 1 , wherein the data conductor has substantially the same planar shape as the semiconductor layer except for a channel portion of the semiconductor layer.
9. A thin film transistor array panel, comprising:
an insulating substrate;
a gate line formed on the substrate;
a plurality of storage electrodes formed on the substrate, each storage
electrode including a plurality of branches;
a gate insulating layer formed on the gate line and the storage electrode;
a semiconductor layer formed on the gate insulating layer;
a data conductor formed on the semiconductor layer;
a passivation layer formed on the data conductor; and
a pixel electrode layer formed on the passivation layer,
wherein at most one of the branches of each storage electrode has an isolated end, and
wherein longitudinal portions of adjacent storage electrodes are connected by connecting portions.
10. The thin film transistor array panel of claim 9 , further comprising a connection bridge having a portion thereof connected to each of the isolated ends of the plurality of storage electrodes and a portion thereof connected to a storage electrode line formed on the substrate.
11. The thin film transistor array panel of claim 9 , wherein each storage electrode further comprises two longitudinal branches and two oblique branches, and the branches of each storage conductor form a closed loop.
12. The thin film transistor array panel of claim 9 , wherein each storage electrode comprises two longitudinal branches connected to three oblique branches, the connected branches forming two closed loops.
13. The thin film transistor array panel of claim 9 , wherein each storage electrode comprises two longitudinal branches connected to four oblique branches, the connected branches forming three closed loops.
14. The thin film transistor array panel of claim 9 , wherein the pixel electrode has a plurality of cutouts, and at least one of the cutouts overlaps the storage electrode.
15. The thin film transistor array panel of claim 9 , wherein the data conductor has substantially the same planar shape as the semiconductor layer except for a channel portion of the semiconductor layer.