PAM-4 data slicer having symmetrical offset
View Patent ↗A PAM-4 data slicer includes first, second, and third comparators which provide first, second, and third thresholds, respectively. Each of the comparators has an offset. The first and third comparators have an offset generating arrangement at their outputs to provide the first and third comparator circuits with symmetrical offsets.
1. A data slicer comprising:
a first differential comparator circuit that establishes a first threshold and that includes first and second output nodes having respective first and second polarities;
a second differential comparator circuit that establishes a second threshold and that includes first and second output nodes having respective first and second polarities; and
a third differential comparator circuit that establishes a third threshold and that includes first and second output nodes having respective first and second polarities;
wherein the second threshold is greater than the first threshold and less than the third threshold,
wherein each of the differential comparator circuits has an offset,
wherein the first and third differential comparator circuits have symmetrical offsets, and
wherein the first output node of the first differential comparator is coupled to the second output node of the third differential comparator.
2. The data slicer of claim 1 wherein:
each of the differential comparator circuits includes first and second branches coupled to the respective first and second output nodes;
the first branch of the first differential comparator includes a first impedance element coupled to the first output node and a second impedance element coupled to the first impedance element at an offset node;
the second branch of the third differential comparator includes a first impedance element coupled to the second output node and a second impedance element coupled to the first impedance element at an offset node; and
the offset node of the first differential comparator is coupled to the offset node of the third differential comparator.
3. The data slicer of claim 2 wherein each impedance element comprises a resistor.
4. The data slicer of claim 1 wherein the first and third thresholds are equally spaced from the second threshold.
5. The data slicer of claim 1 wherein the differential comparator circuits are formed from complimentary metal oxide semiconductor devices.
6. A data slicer comprising:
a first comparator circuit that establishes a first threshold;
a second comparator circuit that establishes a second threshold; and
a third comparator circuit that establishes a third threshold;
wherein the second threshold is greater than the first threshold and less than the third threshold,
wherein each of the comparator circuits has an offset,
wherein the first and third comparator circuits have symmetrical offsets, and
wherein each of the first and third comparator circuits includes a load resistor having a center tap and wherein the load resistor center tap of the first comparator circuit is coupled to the load resistor center tap of the third comparator circuit to provide the first and second comparator circuits with symmetrical offsets.
7. A data slicer comprising:
a first differential comparator circuit that establishes a first threshold and that includes first and second output nodes having respective first and second polarities and an output circuit coupled to the first output node;
a second differential comparator circuit that establishes a second threshold and that includes first and second output nodes having respective first and second polarities and an output circuit coupled to the first output node; and
a third differential comparator circuit that establishes a third threshold and that includes first and second output nodes having respective first and second polarities and an output circuit coupled to the first output node;
wherein the second threshold is greater than the first threshold and less than the third threshold,
wherein each of the differential comparator circuits has an offset,
wherein the first and third differential comparator circuits have output circuits providing symmetrical offsets, and
wherein the output circuit of the first differential comparator is coupled to the output circuit of the third differential comparator.
8. The data slicer of claim 7 wherein the first and third thresholds are equally spaced from the second threshold.
9. The data slicer of claim 7 wherein the differential comparator circuits are formed from complimentary metal oxide semiconductor devices.
10. A data slicer comprising:
a first comparator circuit that establishes a first threshold;
a second comparator circuit that establishes a second threshold; and
a third comparator circuit that establishes a third threshold;
wherein the second threshold is greater than the first threshold and less than the third threshold;
wherein each of the comparator circuits has an offset,
wherein the first and third comparator circuits have output circuits providing symmetrical offsets, and
wherein the output circuit of each of the first and third comparator circuits includes a load resistor having a center tap and wherein the load resistor center tap of the first comparator circuit is coupled to the load resistor center tap of the third comparator circuit to provide the first and second comparator circuits with the symmetrical offsets.
11. An integrated circuit comprising:
a substrate of semiconductor material; and
a data slicer formed in the semiconductor material, the data slicer including,
a first differential comparator circuit that establishes a first threshold and that includes first and second output nodes having respective first and second polarities,
a second differential comparator circuit that establishes a second threshold and that includes first and second output nodes having respective first and second polarities, and
a third differential comparator circuit that establishes a third threshold and that includes first and second output nodes having respective first and second polarities,
wherein the second threshold is greater than the first threshold and less than the third threshold,
wherein each of the differential comparator circuits has an offset,
wherein the first and third differential comparator circuits have symmetrical offsets, and
wherein the first output node of the first differential comparator is coupled to the second output node of the third differential comparator.
12. The integrated circuit of claim 11 wherein the first and third differential comparator circuits have output circuits providing the symmetrical offsets.
13. The integrated circuit of claim 11 wherein the first and third thresholds of the data slicer are equally spaced from the second threshold.
14. The integrated circuit of claim 11 wherein the differential comparator circuits are formed from complimentary metal oxide semiconductor devices.
15. An integrated circuit comprising:
a substrate of semiconductor material; and
a data slicer formed in the semiconductor material, the data slicer including,
a first comparator circuit that establishes a first threshold,
a second comparator circuit that establishes a second threshold, and
a third comparator circuit that establishes a third threshold,
wherein the second threshold is greater than the first threshold and less than the third threshold,
wherein each of the comparator circuits has an offset,
wherein the first and third comparator circuits have symmetrical offsets, and
wherein each of the first and third comparator circuits includes a load resistor having a center tap and wherein the load resistor center tap of the first comparator circuit is coupled to the load resistor center tap of the third comparator circuit to provide the first and second comparator circuits with symmetrical offsets.