Dual key controlled content addressable memory for accessing packet switch data buffer for multicasting data packets
View Patent ↗A data management architecture for a high speed packet switch has a dual key-based content addressable memory (CAM)-based buffer access control mechanism that stores relatively long data packets for delivery to multiple output ports of the switch. The CAM stores multiple address pointer words, each having a key field to identify a data packet, and an address field to identify the address of the location of the packet buffer in which the data packet is stored. During a CAM search, a packet request key is coupled to the key fields of all address pointer words stored in the CAM. The location of the matching key is used to access the key field's companion address field in its address pointer word to access a data packet stored in the packet buffer, and to address fields of all address pointer words stored in the CAM. The CAM outputs a signal that indicates whether or not the buffer address from which the packet has been accessed is free to store new data.
1. A method of interfacing data with a data memory comprising the steps of:
(a) storing said data in said data memory by:
(a1) writing said data into a storage location of said data memory, and
(a2) writing, into a plurality of respective storage regions of a content-addressable memory, respective address pointer words, each of which includes a respective key field that is used to identify said data, and an address field that identifies the address of said storage location of said data memory;
(b) reading said data from said data memory by:
(b1) coupling a key to key fields of address pointer words stored in storage regions of said content-addressable memory, and accessing said address of said storage location of said data memory from the address field of an address pointer word whose key field contains said key;
(b2) reading said data from said storage location of said data memory in accordance with said address accessed in step (b1); and
(c) coupling said address accessed in step (b1) to said content-addressable memory, to determine whether said address of said storage location of said data memory is contained in another address pointer word stored in said content-addressable memory.
2. The method according to claim 1 , wherein steps (b2) and (c) are conducted during a common memory cycle for said content-addressable memory.
3. The method according to claim 1 , wherein step (c) comprises selectively making said storage location of said data memory available for storage of new data, in dependence upon whether or not said address of said storage location of said data memory is contained in another address pointer word stored in said content-addressable memory.
4. The method according to claim 1 , wherein step (a) comprises writing, into plural storage regions of said content-addressable memory, a plurality of address pointer words, each of which contains a respectively different key field used to identify said data, and said address of said storage location of said data memory.
5. The method according to claim 1 , wherein said content-addressable memory comprises a data bit storage cell having a data input through which a data bit is written into said data bit storage cell, a data output through which a data bit is read out of said data bit storage cell, and an address input through which said data bit storage cell is selectively accessed, and a data bit comparator coupled to said data bit storage cell and being configured to determine whether the data bit stored in said data bit storage cell matches a reference data bit during a read cycle for said data bit storage cell.