IP Library Granted Patent US 6,940,350
Granted Patent B2
US 6,940,350 · App. 10/618,507 · Granted Sep 6, 2005

Amplifier and method for canceling nonlinearity in amplifier

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Quick Facts
Patent No.
US 6,940,350
App. No.
10/618,507
Granted
Sep 6, 2005
Kind
B2
Abstract

An amplifier including an amplifier transistor that operates in an active region has main current flowing therethrough according to input voltage, and a linear transistor that is driven by offset positive-polarity input voltage to operate in a linear region and has auxiliary current flowing therethrough. The main current and auxiliary current are added to become output current. The offset positive-polarity voltage corresponds to the sum of AC component of the input voltage and an offset DC voltage. Here, a transistor stacked on the linear transistor is coupled to the amplifier transistor to secure the linear region operation of the linear transistor. The stacked transistor is driven by a voltage having polarity opposite to that of the input voltage.

Claims (40)

1. An amplifier comprising:

a first transistor driven by input voltage;

a second transistor driven by a first voltage, the second transistor being coupled to a first terminal of the first transistor; and

a third transistor stacked on the second transistor and driven by a second voltage, the third transistor being coupled to a second terminal of the first transistor,

wherein the first transistor operates in an active region, and the second transistor operates in a linear region according to the second voltage and the third transistor, and the second voltage is applied when a third voltage having polarity opposite to that of the input voltage passes through an offset DC voltage source that performs AC coupling and determines DC voltage.

2. The amplifier as claimed in claim 1 , wherein the first voltage is applied when the input voltage passes through an offset DC voltage source that performs AC coupling and determines DC voltage.

3. The amplifier as claimed in claim 1 , wherein the second voltage is applied when a voltage applied to a contact node of the first transistor and the third transistor passes through an offset DC voltage source that performs AC coupling and determines DC voltage.

4. The amplifier as claimed in claim 2 , wherein both ends of the offset DC voltage source perform AC coupling when they are both short-circuited.

5. The amplifier as claimed in one of claims 2 , wherein the offset DC voltage source includes a capacitor coupled between both ends thereof and a resistor coupled between a DC voltage source and one end thereof.

6. An amplifier that outputs amplified output current according to input voltage, comprising:

a first transistor operating in an active region, a first current flowing through the first transistor according to the input voltage;

a second transistor driven by a first voltage, a second current flowing through the second transistor; and

a third transistor driven by a second voltage to secure a linear region operation of the second transistor, the third transistor being stacked on the second transistor to be coupled to the output terminal of the first transistor,

wherein the output current includes the first and second currents, and the second voltage corresponds to the sum of an offset DC voltage and an AC component bypassed third voltage having polarity opposite to that of the input voltage.

7. The amplifier as claimed in claim 6 , wherein the first voltage corresponds to the sum of an offset DC voltage and an AC component bypassed input voltage.

8. The amplifier as claimed in claim 6 , wherein the second voltage corresponds to the sum of an offset DC voltage and AC component bypassed voltage of the output terminal of the first transistor.

9. The amplifier as claimed in claim 6 , wherein the second voltage corresponds to voltage at the output terminal of the first transistor.

10. A method for canceling nonlinearity in an amplifier having a first transistor operating in an active region according to input voltage and a second transistor driven by a first voltage, the method comprising:

applying a second voltage to a third transistor stacked on the second transistor to allow the second transistor to operate in a linear region; and

adding a first current flowing through the first transistor and a second current flowing through the second transistor,

and applying the second voltage when a third voltage having polarity opposite to that of the input voltage passes through an offset DC voltage source that performs AC coupling and determines DC voltage.

11. The method as claimed in claim 10 , wherein the first voltage corresponds to the sum of an offset DC voltage and AC component bypassed input voltage.

12. An amplifier comprising:

a first transistor driven by input voltage;

a second transistor driven by a first voltage, the second transistor being coupled to a first terminal of the first transistor; and

a third transistor stacked on the second transistor and driven by a second voltage, the third transistor being coupled to a second terminal of the first transistor, wherein the first transistor operates in an active region, and the second transistor operates in a linear region according to the second voltage and the third transistor, and the second voltage is applied when a voltage applied to a contad node of the first transistor and the third transistor passes through an offset DC voltage source that performs AC coupling and determines DC voltage.

13. The amplifier as claimed in claim 12 , wherein the first voltage is applied when the input voltage passes through an offset DC voltage source that performs AC coupling and determines DC voltage.

14. The amplifier as claimed in claim 12 , wherein the second voltage is applied when a third voltage having polarity opposite to that of the input voltage passes through an offset DC voltage source that performs AC coupling and determines DC voltage.

15. The amplifier as claimed in claim 13 , wherein both ends of the offset DC voltage source perform AC coupling when they are both short-circuited.

16. The amplifier as claimed in one of claims 13 , wherein the offset DC voltage source includes a capacitor coupled between both ends thereof and a resistor coupled between a DC voltage source and one end thereof.

17. An amplifier that outputs amplified output current according to input voltage, comprising:

a first transistor operating in an active region, a first current flowing through the first transistor according to the input voltage;

a second transistor driven by a first voltage, a second current flowing through the second transistor; and

a third transistor driven by a second voltage to secure a linear region operation of the second transistor, the third transistor being stacked on the second transistor to be coupled to the output terminal of the first transistor,

wherein the output current includes the first and second currents, and the second voltage corresponds to the sum of an offset DC voltage and AC component bypassed voltage of the output terminal of the first transistor.

18. An amplifier that outputs amplified output current according to input voltage, comprising:

a first transistor operating in an active region, a first current flowing through the first transistor according to the input voltage;

a second transistor driven by a first voltage, a second current flowing through the second transistor; and

a third transistor driven by a second voltage to secure a linear region operation of the second transistor, the third transistor being stacked on the second transistor to be coupled to the output terminal of the first transistor,

wherein the output current includes the first and second currents, and the second voltage corresponds to voltage at the output terminal of the first transistor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2012
From: IPG ELECTRONICS 502 LIMITED; ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
To: PENDRAGON ELECTRONICS AND TELECOMMUNICATIONS RESEARCH LLC
Reel/Frame 028611/0643 →
ASSIGNMENT OF ONE HALF (1/2) OF ALL OF ASSIGNORS' RIGHT, TITLE AND INTEREST Recorded Nov 3, 2009
From: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
To: IPG ELECTRONICS 502 LIMITED
Reel/Frame 023456/0363 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2003
From: YOUN, YONG-SIK; YU, HYUN-KYU; PARK, MUN-YANG
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 014290/0375 →