Adaptive noise filtering and equalization for optimal high speed multilevel signal decoding
A Signal Conditioning Filter (SCF) and a Signal Integrity Unit (SIU) address the coupled problem of equalization and noise filtering in order to improve signal fidelity for decoding. Specifically, a received signal can be filtered in a manner to optimize the signal fidelity even in the presence of both significant (large magnitudes of) ISI and noise. The present invention can provide an adaptive method that continuously monitors a signal fidelity measure. Monitoring the fidelity of a multilevel signal can be performed by external means such as by the SIU. A received signal y(t) can be “conditioned” by application of a filter with an electronically adjustable impulse response g(t). A resulting output z(t) can then be interrogated to characterize the quality of the conditioned signal. This fidelity measure q(t) can be used to adjust the filter response to maximize the fidelity measure of the conditioned signal.
1. A system for processing digital signals comprising symbols propagated according to a period, the system comprising:
a signal conditioning filter comprising a first stage for mitigating degradations of a digital signal that occur according to a first time scale, the first stage comprising a linear tapped-delay line filter tuned to the first time scale, the first time scale comprising a fraction of the period at which the symbols are propagated, and a second stage for removing signal distortions that occur according to a second time scale, the second stage comprising a linear tapped-delay line filter tuned to the second time scale, the second time scale being different than the first time scale and comprising a magnitude at least equal to the period at which the symbols are propagated; and
a signal integrity unit for controlling the signal conditioning filter by maximizing fidelity of the digital signals.
2. The system of claim 1 , wherein the signal conditioning filter comprises a coefficient amplifier, the coefficient amplifier comprising a Gilbert cell multiplier.
3. The system of claim 1 , wherein each tapped delay-line filter comprises LC circuits.
4. The system of claim 1 , wherein delays are distributed across both input and output branches of each tapped delay-line filter.
5. The system of claim 1 , wherein parasitic capacitances from one of an input and output of each tapped-delay line filter are absorbed into an LC design circuit and are used to implement the delay.
6. The system of claim 1 , wherein the digital signals comprise binary signals.
7. The system of claim 1 , wherein the digital signals comprise multilevel signals.
8. The system of claim 1 , wherein the first and second stages comprise various signal pats of different lengths where time delays produced by the signal paths are re-used.
9. A system for processing digital signals comprising:
a first filter stage comprising a first linear tapped-delay line filter tuned to a first time constant, the first time constant comprising a value that is less than a symbol period, for compensating for signal distortions tat occur within a single symbol period and for integrating over less than a symbol period in order to substantially reduce at least one of ringing, jitter, and noise; and
a second filter stage comprising a second linear tapped-delay line filter tuned to a second time constant, the first time constant being smaller than the second time constant and the second time constant comprising value at least equal to a symbol period, the second filter stage for removing inter-symbol interference (ISI).
10. The system of claim 9 , wherein each filter comprises a coefficient amplifier, the coefficient amplifier comprising a Gilbert cell multiplier.
11. The system of claim 9 , wherein each tapped delay-line filter comprises LC circuits.
12. The system of claim 9 , wherein delays are distributed across both input and output branches of each tapped delay-line filter.
13. The system of claim 9 , wherein parasitic capacitances from one of an input and output of each tapped-delay line filter are absorbed into the LC design circuit and are used to implement the delay.
14. The system of claim 9 , wherein the digital signals comprise binary signals.
15. The system of claim 9 , wherein the digital signals comprise multilevel signals.
16. The system of claim 9 , wherein the first and second filtering stages form part of a unit for receiving digital signals.
17. The system of claim 9 , wherein the first and second filtering stages form part of a unit for transmitting digital signals.
18. A system for processing digital signals comprising symbols propagated according to a period, the system comprising:
a cascade of two linear filters, where each filter comprises a series of variable gain amplifiers connected by delay elements, each delay element for a respective filter having a same delay value, each linear filter equalizing a particular frequency band of a multilevel signal;
the delay elements in the first filter being tuned to a fraction of the symbol period at which the symbols are propagated for compensating for signal distortions that occur within a single symbol period and for integrating over less than a symbol period in order to substantially reduce at least one of ringing, jitter, and noise;
the delay elements in the second filter being tuned to a magnitude at least equal to the symbol period at which symbols are propagated for mitigating degradations that occur according to the period.
19. The system of claim 18 , wherein each variable gain amplifier comprises a Gilbert Cell multiplier.
20. The system of claim 18 , wherein the delay elements of the first and second filters comprise delay lines.
21. The system of claim 18 , wherein the delay elements of the first and second filters comprise delay lines that include LC circuits.
22. The system of claim 18 , further comprising a signal integrity unit for controlling each filter.
23. The system of claim 22 , wherein the signal integrity unit measures fidelity of a filtered signal, each filter further comprising a variable gain coefficient amplifier, and gains of each variable gain coefficient amplifier are controlled to maximize fidelity measured byte signal integrity unit.