Ferroelectric memory device and method for reading data from the same
View Patent ↗A ferroelectric memory device includes a plurality of bit line pairs, a plurality of sense amplifiers, a plurality of memory cells, a plurality of reference cells, and a control circuit. Each of the bit line pairs is composed of first and second bit lines. Each of the sense amplifiers amplifies a potential difference across the corresponding bit line pair. The memory cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. The reference cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. In addition, each of the reference cells on each of the bit line pairs retains data different from data of a reference cell on the adjacent bit line pair. The control circuit drives the sense amplifiers, the memory cells, and the reference cells. During the drive of the sense amplifier, the control circuit inactivates a reference word line connected to the reference cell.
1. A ferroelectric memory device comprising:
a plurality of bit line pairs each of which is composed of first and second bit lines;
a plurality of sense amplifiers each for amplifying a potential difference across the corresponding bit line pair;
a plurality of memory cells provided for the bit line pairs, respectively, each of the memory cells being composed of a first ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the first ferroelectric capacitor and whose drain is connected to the first bit line;
a plurality of reference cells provided for the bit line pairs, respectively, each of the reference cells being composed of a second ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the second ferroelectric capacitor and whose drain is connected to the second bit line;
a word line connecting sates of the transistors of the memory cells;
a reference word line connecting gates of the transistors of the reference cells;
a cell plate line connecting second electrodes of the ferroelectric capacitors of the memory cells;
a reference cell plate line connecting second electrodes of the ferroelectric capacitors of the reference cells;
a control circuit for controlling operations of the memory cells, the reference cells, and the sense amplifiers; and
a switch circuit connecting the second bit lines included in adjacent bit line pairs of the plurality of bit line pairs,
wherein the control circuit inactivates the reference word line during the drive of the sense amplifiers,
wherein the control circuit stops the drive of the switch circuit during the drive of the sense amplifiers, and
wherein the control circuit performs successive actions of:
driving the switch circuit and activating the word line, the cell plate line, the reference word line and the reference cell plate line;
inactivating the cell plate line and the reference cell plate line;
inactivating the reference word line;
stopping the drive of the switch circuit; and
driving the sense amplifiers.
2. A ferroelectric memory device comprising:
a plurality of bit line pairs each of which is composed of first and second bit lines;
a plurality of sense amplifiers each for amplifying a potential difference across the corresponding bit line pair;
a plurality of memory cells provided for the bit line pairs, respectively, each of the memory cells being composed of a first ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the first ferroelectric capacitor and whose drain is connected to the first bit line;
a plurality of reference cells provided for the bit line pairs, respectively, each of the reference cells being composed of a second ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the second ferroelectric capacitor and whose drain is connected to the second bit line;
a word line connecting gates of the transistors of the memory cells;
a reference word line connecting gates of the transistors of the reference cells;
a cell plate line connecting second electrodes of the ferroelectric capacitors of the memory cells;
a reference cell plate line connecting second electrodes of the ferroelectric capacitors of the reference cells;
a control circuit for controlling operations of the memory cells, the reference cells, and the sense amplifiers; and
a switch circuit connecting the second bit lines included in adjacent bit line pairs of the plurality of bit line pairs,
wherein the control circuit inactivates the reference word line during the drive of the sense amplifiers,
wherein the control circuit stops the drive of the switch circuit during the drive of the sense amplifiers, and
wherein the control circuit performs successive actions of:
driving the switch circuit and activating the word line, the cell plate line, the reference word line and the reference cell plate line;
inactivating the cell plate line and the reference cell plate line;
stopping the drive of the switch circuit;
inactivating the reference word line; and
driving the sense amplifiers.
3. A ferroelectric memory device comprising:
a plurality of bit line pairs each of which is composed of first and second bit lines;
a plurality of sense amplifiers each for amplifying a potential difference across the corresponding bit line pair;
a plurality of memory cells provided for the bit line pairs, respectively, each of the memory cells being composed of a first ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the first ferroelectric capacitor and whose drain is connected to the first bit line;
a plurality of reference cells provided for the bit line pairs, respectively, each of the reference cells being composed of a second ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the second ferroelectric capacitor and whose drain is connected to the second bit line;
a word line connecting gates of the transistors of the memory cells;
a reference word line connecting gates of the transistors of the reference cells;
a cell plate line connecting second electrodes of the ferroelectric capacitors of the memory cells;
a reference cell plate line connecting second electrodes of the ferroelectric capacitors of the reference cells;
a control circuit for controlling operations of the memory cells, the reference cells, and the sense amplifiers; and
a switch circuit connecting the second bit lines included in adjacent bit line pairs of the plurality of bit line pairs,
wherein the control circuit inactivates the reference word line during the drive of the sense amplifiers,
wherein the control circuit stops the drive of the switch circuit during the drive of the sense amplifiers, and
wherein the control circuit performs successive actions of:
driving the switch circuit and activating the word line, the cell plate line, the reference word line and the reference cell plate line;
inactivating the reference word line;
stopping the drive of the switch circuit;
inactivating the cell plate line and the reference cell plate line; and
driving the sense amplifiers.
4. A ferroelectric memory device comprising:
a plurality of bit line pairs each of which is composed of first and second bit lines;
a plurality of sense amplifiers each for amplifying a potential difference across the corresponding bit line pair;
a plurality of memory cells provided for the bit line pairs, respectively, each of the memory cells being composed of a first ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the first ferroelectric capacitor and whose drain is connected to the first bit line;
a plurality of reference cells provided for the bit line pairs, respectively, each of the reference cells being composed of a second ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the second ferroelectric capacitor and whose drain is connected to the second bit line;
a word line connecting gates of the transistors of the memory cells;
a reference word line connecting gates of the transistors of the reference cells;
a cell plate line connecting second electrodes of the ferroelectric capacitors of the memory cells;
a reference cell plate line connecting second electrodes of the ferroelectric capacitors of the reference cells;
a control circuit for controlling operations of the memory cells, the reference cells, and the sense amplifiers; and
a switch circuit connecting the second bit lines included in adjacent bit line pairs of the plurality of bit line pairs,
wherein the control circuit inactivates the reference word line during the drive of the sense amplifiers,
wherein the control circuit stops the drive of the switch circuit during the drive of the sense amplifiers, and
wherein the control circuit performs successive actions of:
driving the switch circuit and activating the word line, the cell plate line, the reference word line and the reference cell plate line;
stopping the drive of the switch circuit;
inactivating the reference word line;
inactivating the cell plate line and the reference cell plate line; and
driving the sense amplifiers.
5. A method for reading data from a ferroelectric memory device, wherein the ferroelectric memory device includes:
a plurality of bit line pairs each of which is composed of first and second bit lines;
a plurality of sense amplifiers each for amplifying a potential difference across the corresponding bit line pair;
a plurality of memory cells provided for the bit line pairs, respectively, each of the memory cells being composed of a first ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the first ferroelectric capacitor and whose drain is connected to the first bit line;
a plurality of reference cells provided for the bit line pairs, respectively, each of the reference cells being composed of a second ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the second ferroelectric capacitor and whose drain is connected to the second bit line;
a word line connecting gates of the transistors of the memory cells;
a reference word line connecting gates of the transistors of the reference cells;
a cell plate line connecting second electrodes of the ferroelectric capacitors of the memory cells;
a reference cell plate line connecting second electrodes of the ferroelectric capacitors of the reference cells;
a control circuit for controlling operations of the memory cells, the reference cells, and the sense amplifiers; and
a switch circuit connecting the second bit lines included in adjacent bit line pairs of the plurality of bit line pairs;
the method comprising:
a first step of activating the word line and the reference word line;
a second step of activating the cell plate line and the reference cell plate line for a predetermined period of time;
a third step of activating a switch control signal for driving the switch circuit;
a fourth step of inactivating the reference word line after the first step;
a fifth step of inactivating the switch control signal after the third step; and
a sixth step of driving the sense amplifier for a predetermined period of time after the fourth step,
wherein the second step is kept on until after the initiation of the sixth step.