Semiconductor processing device
View Patent ↗A useful semiconductor processing device (LSI) is capable of implementing the precise setting of signals at the final stage of user system development and enabling the user to build a logic circuit in the device in a very short time. The LSI includes a CPU, a flash memory which is a nonvolatile memory, a programmable logic which is a SRAM-type field programmable gate array, and a configuration circuit which implements the logic circuit configuration operation. At the event of power-on reset, logic building data stored in the flash memory is transferred to the programmable logic to establish a logic circuit in it under control of the configuration circuit, so that the logic circuit built in the programmable logic can be used immediately after the power-on reset of the device.
1. A semiconductor processing device formed on a semiconductor substrate, comprising:
a central processing unit;
an SRAM-type field programmable gate array which establishes a logic circuit based on logic building data written thereto;
a nonvolatile memory which stores the logic building data establishing the logic circuit in the SRAM-type field programmable gate array; and
a configuration circuit which implements a configuration operation for said SRAM-type field programmable gate array by using the logic building data stored in said nonvolatile memory,
wherein said configuration circuit has a function of transferring the logic building data in said nonvolatile memory to said SRAM-type field programmable gate array at the event of power-on reset, and
wherein said configuration circuit includes a function of releasing an internal reset signal on completion of configuration operation.
2. A semiconductor processing device according to claim 1 , wherein said nonvolatile memory includes an exclusive bus for transferring the logic building data to said configuration circuit at the time of configuration operation.
3. A semiconductor processing device formed on a semiconductor substrate, comprising:
a central processing unit;
an SRAM-type field programmable gate array which establishes a logic circuit based on logic building data written thereto;
a nonvolatile memory which stores the logic building data establishing the logic circuit in the SRAM-type field programmable gate array;
a configuration circuit which implements a configuration operation for said SRAM-type field programmable gate array by using the logic building data stored in said nonvolatile memory;
said configuration circuit having a function of transferring the logic building data in said nonvolatile memory to said SRAM-type field programmable gate array at the event of power-on reset; and
a terminal which indicates completion of the configuration operation by said configuration circuit,
the semiconductor processing device further having a function of initiating a peripheral semiconductor device through said terminal.
4. A semiconductor processing device formed on a semiconductor substrate, comprising:
a central processing unit;
an SRAM-type field programmable gate array which establishes a logic circuit based on logic building data written thereto;
a nonvolatile memory which stores the logic building data establishing the logic circuit in the SRAM-type field programmable gate array; and
a configuration circuit which implements a configuration operation for said SRAM-type field programmable gate array by using the logic building data stored in said nonvolatile memory,
wherein said configuration circuit has a function of transferring the logic building data in said nonvolatile memory to said SRAM-type field programmable gate array at the event of power-on reset, and
wherein said nonvolatile memory comprises a flash memory.
5. A semiconductor processing device formed on a semiconductor substrate, comprising:
a central processing unit;
an SRAM-type field programmable gate array which establishes a logic circuit based on logic building data written thereto;
a nonvolatile memory which stores the logic building data establishing the logic circuit in the SRAM-type field programmable gate array; and
a configuration circuit which implements a configuration operation for said SRAM-type field programmable gate array by using the logic building data stored in said nonvolatile memory,
wherein said configuration circuit has a function of reconstructing, during the operation of said central processing unit, part of the logic building data in said SRAM-type field programmable gate array which has been transferred from said nonvolatile memory.
6. A semiconductor processing device according to claim 5 wherein said nonvolatile memory comprises a flash memory.
7. A semiconductor processing device formed on a semiconductor substrate, comprising:
a central processing unit;
an SRAM-type field programmable gate array which establishes a logic circuit based on logic building data written thereto;
a nonvolatile memory which stores the logic building data establishing the logic circuit in the SRAM-type field programmable gate array;
a configuration circuit which implements a configuration operation for said SRAM-type field programmable gate array by using the logic building data stored in said nonvolatile memory; and
a plurality of terminals in correspondence to the logic building data of said SRAM-type field programmable gate array,
wherein said configuration circuit has a function of selecting logic building data in said nonvolatile memory in correspondence to said terminals and transferring the selected data to said SRAM-type field programmable gate array.
8. A semiconductor processing device according to claim 7 , wherein said nonvolatile memory comprises a flash memory.
9. A semiconductor processing device formed on a semiconductor substrate, comprising:
a central processing unit;
an SRAM-type field programmable gate array which establishes a logic circuit based on logic building data written thereto;
a nonvolatile memory which stores the logic building data establishing the logic circuit in the SRAM-type field programmable gate array; and
a configuration circuit which implements a configuration operation for said SRAM-type field programmable gate array by using the logic building data stored in said nonvolatile memory,
wherein said configuration circuit has a register which stores a plurality of data corresponding to the logic building data of said SRAM-type field programmable gate array, and
wherein said configuration circuit includes a function of selecting logic building data in said nonvolatile memory in correspondence to the data in said register and transferring the selected data to said SRAM-type field programmable gate array.
10. A semiconductor processing device according to claim 9 , wherein said nonvolatile memory comprises a flash memory.