Method for suppressing even order harmonics in a device that utilizes transconductors
View Patent ↗A method for calibrating a low pass filter is disclosed. The low pass filter comprises a plurality of transconductor cells. The method comprises generating a test signal to the low pass filter and suppressing even-order harmonics due to transistor mismatches within the plurality of transconductor cells. By adding a small number of transistors, the mismatch-induced even order harmonics can be greatly reduced. Even-order harmonics are minimized through the application of a control voltage. A method for calibrating against transistor mismatch utilizing a CMOS transconductor that is based on the regulated cascode topology is disclosed. The method is designed to provide suppression of the even-order harmonics, a very small increase in power and a silicon area of the transconductor cell. A well-defined offset is provided by biasing one of the mismatched transistors.
1. A method for calibrating a device, the device comprising a plurality of transconductor cells, the method comprising the steps of:
(a) generating a test signal to the device; and
(b) suppressing even-order harmonics due to transistor mismatches within the plurality of transconductor cells, wherein the suppressing step (b) comprises the step of (b 1 ) introducing an offset voltage on an amplifier in the plurality of transconductor cells that controls the drain to source voltage of the input transistors of the cells.
2. The method of claim 1 , wherein the offset voltage is controlled by a DSP in order to minimize the even order harmonics upon the application of the test signal on the device.
3. The method of claim 1 wherein the device comprises a second order low pass filter.
4. The method of claim 1 wherein the test signal comprises a sinusoidal test signal.
5. A calibration system comprising a device, the device including a plurality of transconductor cells; and
a digital signal processor (DSP), the DSP for generating a test signal to the device and for suppressing even order harmonics due to transistor mismatches within the plurality of transconductor cells, wherein the DSP introduces an offset voltage to each amplifier in a plurality of transconductor cells that control the drain to source voltage of the input transistors of the cells.
6. The system of claim 5 wherein the device comprises a second order low pass filter.
7. The system of claim 5 wherein the DSP controls the offset voltage in order to minimize the even order harmonics upon the application of the test signal on the device.
8. The system of claim 5 wherein the test signal comprises a sinusoidal test signal.