Circuits and methods for data multiplexing
View Patent ↗A method and apparatus for data multiplexing is capable of high-speed operation with acceptable timing margins and has reduced sensitivity to supply voltage, temperature, manufacturing and other variations. One implementation relates to a data multiplexer that has no significant speed limitation associated with the clock-to-data delay of data latches, flip-flops, etc. In one implementation, clock-to-data delay is compensated for by introducing a delay-compensator in the clock line that drives a selector stage of the multiplexer. In one such implementation, a timing relationship is established between clock and data waveforms by timing the data waveforms with a first in-phase clock and operating the delay-compensated selector clock line with a second clock, which is delayed with respect to the first clock. The second clock can have a quadrature-phase delay with respect to the in-phase clock.
1. A circuit for multiplexing a plurality of data signals into an output data stream comprising:
a plurality of circuit elements, wherein a transition of each circuit element of said plurality of circuit elements is clocked by a first clock signal received from a source other than one of the plurality of circuit elements, wherein an output of each circuit element of said plurality of circuit elements comprises an individual data signal of said plurality of data signals and wherein said first clock signal is in-phase with said transition;
a selector coupled to said plurality of circuit elements for receiving each of the individual output data signals from the plurality of circuit elements and for sequentially selecting each of said individual data signals to generate said output data stream as the output of the selector, wherein said selector is clocked to control said selecting by a second clock signal received from a source other than one of the plurality of circuit elements, wherein said second clock signal is out of phase with respect to said first clock signal by a fixed offset; and
a compensator that is separate from the plurality of circuit elements coupled to said selector for compensating for a clock-to-data delay corresponding to said transition of each said circuit elements, wherein said second clock signal is transmitted to said selector through said compensator, and wherein said compensator retards said second clock signal to said selector by a compensating delay corresponding to said clock-to-data delay.
2. The circuit as recited in claim 1 wherein said fixed offset comprises a quadrature offset.
3. The circuit as recited in claim 1 wherein said fixed offset comprises a delay.
4. The circuit as recited in claim 3 wherein said delay comprises a quadrature delay.
5. The circuit as recited in claim 3 wherein said delay comprises a propagation delay.
6. The circuit as recited in claim 5 further comprising a section of a transmission medium coupled to said selector wherein said section comprises a particular length, wherein said particular length corresponds to said propagation delay.
7. The circuit as recited in claim 1 further comprising a clock generator coupled to said selector for generating said fixed offset.
8. The circuit as recited in claim 7 wherein said clock generator comprises a coupled oscillator circuit.
9. The circuit as recited in claim 7 wherein said clock generator comprises a divide-by-two circuit.
10. The circuit as recited in claim 1 wherein a part of said plurality of circuit elements comprises a flip-flop.
11. In a circuit comprising a plurality of circuit elements each for providing a data signal with transitions in response to a clock signal and a selector coupled to said plurality of circuit elements for selecting said data signals for an output data stream, a method for multiplexing a plurality of said data signals into an output data stream comprising:
providing first and second clock signals received from a source other than one of the plurality of circuit elements, wherein said second clock signal is out-of-phase with respect to said first clock signal by a fixed offset;
clocking said circuit elements with said first clock signal to control said transitions of said data signal;
clocking said selector with said second clock to sequentially select a plurality of said data signals that are received as input for the selector for said output data stream and wherein said second clock is received as a separate input from the plurality of said data signals; and
delaying said second clock signal by a compensating delay corresponding to a delay from said first clock signal to said transitions of said circuit elements.
12. The method as recited in claim 11 wherein said fixed offset comprises a quadrature offset.
13. The method as recited in claim 11 wherein said fixed offset comprises a delay.
14. The method as recited in claim 13 wherein said delay comprises a quadrature delay.
15. The method as recited in claim 13 wherein said delay is generated by a clock generator coupled to said selector.
16. The method as recited in claim 15 wherein said clock generator comprises a coupled oscillator circuit.
17. The method as recited in claim 15 wherein said clock generator comprises a divide-by-two circuit.
18. The method as recited in claim 13 wherein said delay comprises a propagation delay.
19. The method as recited in claim 18 further comprising a section of a transmission medium coupled to said selector wherein said section comprises a particular length, wherein said particular length corresponds to said propagation delay.
20. A system for multiplexing a plurality of data signals into an output data stream comprising:
a plurality of circuit elements, wherein a transition of each circuit element of said plurality of circuit elements is clocked by a first clock signal received from a source other than one of the plurality of circuit elements, wherein an output of each circuit element of said plurality of circuit elements comprises an individual data signal of said plurality of data signals and wherein said first clock signal is in-phase with said transition;
a selector coupled to said plurality of circuit elements for receiving each of the individual output data signals from the plurality of circuit elements and for sequentially selecting each of said individual data signals to generate said output data stream as the output of the selector, wherein said selector is clocked to control said selecting by a second clock signal received from a source other than one of the plurality of circuit elements, wherein said second clock signal is out of phase with respect to said first clock signal by a fixed quadrature delay; and
a compensator that is separate from the plurality of circuit elements coupled to said selector for compensating for a clock-to-data delay corresponding to said transition of each said circuit elements, wherein said second clock signal is transmitted to said selector through said compensator, and wherein said compensator retards said second clock signal to said selector by a compensating delay corresponding to said clock-to-data delay.
21. The system as recited in claim 20 further comprising a clock generator coupled to said selector for generating said fixed quadrature delay.
22. The system as recited in claim 21 wherein said clock generator comprises a circuit selected from the group consisting essentially of a coupled oscillator circuit and a divide-by-two circuit.
23. The system as recited in claim 21 wherein said quadrature delay comprises a propagation delay.
24. The system as recited in claim 23 wherein said clock generator comprises a section of a transmission medium coupled to said selector wherein said section comprises a particular length, wherein said particular length corresponds to said propagation delay.
25. The system as recited in claim 20 wherein a part of said plurality of circuit elements comprises a flip-flop.